SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.97 | 100.00 | 71.88 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
98.68 | 100.00 | 94.74 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
96.83 | 100.00 | 92.31 | 95.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.16 | 94.16 | 96.15 | 96.90 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 93.64 | 100.00 | 90.00 | 90.91 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.36 | 95.00 | 87.10 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.36 | 95.00 | 87.10 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.37 | 95.00 | 89.47 | 85.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
98.68 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T9 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
98.68 | 94.74 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
98.68 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 6 | 6 | 100.00 | 6 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 6 | 6 | 100.00 | 6 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 2147483647 | 227478903 | 0 | 0 |
DepthKnown_A | 2147483647 | 2147483647 | 0 | 0 |
RvalidKnown_A | 2147483647 | 2147483647 | 0 | 0 |
WreadyKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 1662898564 | 35138862 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 7932 | 7932 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 227478903 | 0 | 0 |
T1 | 159110 | 7769 | 0 | 0 |
T2 | 124500 | 6402 | 0 | 0 |
T3 | 196080 | 14385 | 0 | 0 |
T4 | 1119260 | 72933 | 0 | 0 |
T5 | 1664390 | 131792 | 0 | 0 |
T9 | 193100 | 14826 | 0 | 0 |
T10 | 92160 | 5301 | 0 | 0 |
T11 | 132570 | 6934 | 0 | 0 |
T12 | 135590 | 7322 | 0 | 0 |
T13 | 983510 | 70495 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 159110 | 156680 | 0 | 0 |
T2 | 124500 | 121630 | 0 | 0 |
T3 | 196080 | 193470 | 0 | 0 |
T4 | 1119260 | 1108350 | 0 | 0 |
T5 | 1664390 | 1650100 | 0 | 0 |
T9 | 193100 | 190400 | 0 | 0 |
T10 | 92160 | 89880 | 0 | 0 |
T11 | 132570 | 129810 | 0 | 0 |
T12 | 135590 | 132530 | 0 | 0 |
T13 | 983510 | 970300 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 159110 | 156680 | 0 | 0 |
T2 | 124500 | 121630 | 0 | 0 |
T3 | 196080 | 193470 | 0 | 0 |
T4 | 1119260 | 1108350 | 0 | 0 |
T5 | 1664390 | 1650100 | 0 | 0 |
T9 | 193100 | 190400 | 0 | 0 |
T10 | 92160 | 89880 | 0 | 0 |
T11 | 132570 | 129810 | 0 | 0 |
T12 | 135590 | 132530 | 0 | 0 |
T13 | 983510 | 970300 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 159110 | 156680 | 0 | 0 |
T2 | 124500 | 121630 | 0 | 0 |
T3 | 196080 | 193470 | 0 | 0 |
T4 | 1119260 | 1108350 | 0 | 0 |
T5 | 1664390 | 1650100 | 0 | 0 |
T9 | 193100 | 190400 | 0 | 0 |
T10 | 92160 | 89880 | 0 | 0 |
T11 | 132570 | 129810 | 0 | 0 |
T12 | 135590 | 132530 | 0 | 0 |
T13 | 983510 | 970300 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1662898564 | 35138862 | 0 | 0 |
T1 | 63644 | 4149 | 0 | 0 |
T2 | 49800 | 3454 | 0 | 0 |
T3 | 78432 | 4441 | 0 | 0 |
T4 | 447704 | 15495 | 0 | 0 |
T5 | 665756 | 23966 | 0 | 0 |
T9 | 77240 | 5424 | 0 | 0 |
T10 | 36864 | 2281 | 0 | 0 |
T11 | 53028 | 3244 | 0 | 0 |
T12 | 54236 | 3804 | 0 | 0 |
T13 | 393404 | 19411 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7932 | 7932 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 415724641 | 18105166 | 0 | 0 |
DepthKnown_A | 415724641 | 414852436 | 0 | 0 |
RvalidKnown_A | 415724641 | 414852436 | 0 | 0 |
WreadyKnown_A | 415724641 | 414852436 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 415724641 | 18105166 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 18105166 | 0 | 0 |
T1 | 15911 | 4107 | 0 | 0 |
T2 | 12450 | 3048 | 0 | 0 |
T3 | 19608 | 3897 | 0 | 0 |
T4 | 111926 | 14992 | 0 | 0 |
T5 | 166439 | 22426 | 0 | 0 |
T9 | 19310 | 4648 | 0 | 0 |
T10 | 9216 | 1987 | 0 | 0 |
T11 | 13257 | 2498 | 0 | 0 |
T12 | 13559 | 3134 | 0 | 0 |
T13 | 98351 | 18677 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 18105166 | 0 | 0 |
T1 | 15911 | 4107 | 0 | 0 |
T2 | 12450 | 3048 | 0 | 0 |
T3 | 19608 | 3897 | 0 | 0 |
T4 | 111926 | 14992 | 0 | 0 |
T5 | 166439 | 22426 | 0 | 0 |
T9 | 19310 | 4648 | 0 | 0 |
T10 | 9216 | 1987 | 0 | 0 |
T11 | 13257 | 2498 | 0 | 0 |
T12 | 13559 | 3134 | 0 | 0 |
T13 | 98351 | 18677 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 55194424 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 55194424 | 0 | 0 |
T1 | 15911 | 905 | 0 | 0 |
T2 | 12450 | 709 | 0 | 0 |
T3 | 19608 | 933 | 0 | 0 |
T4 | 111926 | 5216 | 0 | 0 |
T5 | 166439 | 9815 | 0 | 0 |
T9 | 19310 | 857 | 0 | 0 |
T10 | 9216 | 755 | 0 | 0 |
T11 | 13257 | 883 | 0 | 0 |
T12 | 13559 | 838 | 0 | 0 |
T13 | 98351 | 6253 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 45300137 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 45300137 | 0 | 0 |
T1 | 15911 | 905 | 0 | 0 |
T2 | 12450 | 765 | 0 | 0 |
T3 | 19608 | 4039 | 0 | 0 |
T4 | 111926 | 23503 | 0 | 0 |
T5 | 166439 | 44098 | 0 | 0 |
T9 | 19310 | 3844 | 0 | 0 |
T10 | 9216 | 755 | 0 | 0 |
T11 | 13257 | 962 | 0 | 0 |
T12 | 13559 | 921 | 0 | 0 |
T13 | 98351 | 19289 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 23030847 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 23030847 | 0 | 0 |
T1 | 15911 | 2 | 0 | 0 |
T2 | 12450 | 14 | 0 | 0 |
T3 | 19608 | 20 | 0 | 0 |
T4 | 111926 | 29 | 0 | 0 |
T5 | 166439 | 92 | 0 | 0 |
T9 | 19310 | 28 | 0 | 0 |
T10 | 9216 | 14 | 0 | 0 |
T11 | 13257 | 28 | 0 | 0 |
T12 | 13559 | 24 | 0 | 0 |
T13 | 98351 | 40 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 15836155 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 15836155 | 0 | 0 |
T1 | 15911 | 2 | 0 | 0 |
T2 | 12450 | 70 | 0 | 0 |
T3 | 19608 | 82 | 0 | 0 |
T4 | 111926 | 120 | 0 | 0 |
T5 | 166439 | 409 | 0 | 0 |
T9 | 19310 | 122 | 0 | 0 |
T10 | 9216 | 14 | 0 | 0 |
T11 | 13257 | 107 | 0 | 0 |
T12 | 13559 | 107 | 0 | 0 |
T13 | 98351 | 158 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 23514496 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 23514496 | 0 | 0 |
T1 | 15911 | 903 | 0 | 0 |
T2 | 12450 | 695 | 0 | 0 |
T3 | 19608 | 913 | 0 | 0 |
T4 | 111926 | 5187 | 0 | 0 |
T5 | 166439 | 9723 | 0 | 0 |
T9 | 19310 | 829 | 0 | 0 |
T10 | 9216 | 741 | 0 | 0 |
T11 | 13257 | 855 | 0 | 0 |
T12 | 13559 | 814 | 0 | 0 |
T13 | 98351 | 6213 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 418739337 | 29463982 | 0 | 0 |
DepthKnown_A | 418739337 | 417813632 | 0 | 0 |
RvalidKnown_A | 418739337 | 417813632 | 0 | 0 |
WreadyKnown_A | 418739337 | 417813632 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1322 | 1322 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 29463982 | 0 | 0 |
T1 | 15911 | 903 | 0 | 0 |
T2 | 12450 | 695 | 0 | 0 |
T3 | 19608 | 3957 | 0 | 0 |
T4 | 111926 | 23383 | 0 | 0 |
T5 | 166439 | 43689 | 0 | 0 |
T9 | 19310 | 3722 | 0 | 0 |
T10 | 9216 | 741 | 0 | 0 |
T11 | 13257 | 855 | 0 | 0 |
T12 | 13559 | 814 | 0 | 0 |
T13 | 98351 | 19131 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 418739337 | 417813632 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1322 | 1322 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 415724641 | 16277014 | 0 | 0 |
DepthKnown_A | 415724641 | 414852436 | 0 | 0 |
RvalidKnown_A | 415724641 | 414852436 | 0 | 0 |
WreadyKnown_A | 415724641 | 414852436 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 415724641 | 16277014 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 16277014 | 0 | 0 |
T1 | 15911 | 20 | 0 | 0 |
T2 | 12450 | 196 | 0 | 0 |
T3 | 19608 | 262 | 0 | 0 |
T4 | 111926 | 237 | 0 | 0 |
T5 | 166439 | 724 | 0 | 0 |
T9 | 19310 | 374 | 0 | 0 |
T10 | 9216 | 140 | 0 | 0 |
T11 | 13257 | 359 | 0 | 0 |
T12 | 13559 | 323 | 0 | 0 |
T13 | 98351 | 347 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 16277014 | 0 | 0 |
T1 | 15911 | 20 | 0 | 0 |
T2 | 12450 | 196 | 0 | 0 |
T3 | 19608 | 262 | 0 | 0 |
T4 | 111926 | 237 | 0 | 0 |
T5 | 166439 | 724 | 0 | 0 |
T9 | 19310 | 374 | 0 | 0 |
T10 | 9216 | 140 | 0 | 0 |
T11 | 13257 | 359 | 0 | 0 |
T12 | 13559 | 323 | 0 | 0 |
T13 | 98351 | 347 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 415724641 | 551205 | 0 | 0 |
DepthKnown_A | 415724641 | 414852436 | 0 | 0 |
RvalidKnown_A | 415724641 | 414852436 | 0 | 0 |
WreadyKnown_A | 415724641 | 414852436 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 415724641 | 551205 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 551205 | 0 | 0 |
T1 | 15911 | 20 | 0 | 0 |
T2 | 12450 | 140 | 0 | 0 |
T3 | 19608 | 200 | 0 | 0 |
T4 | 111926 | 146 | 0 | 0 |
T5 | 166439 | 407 | 0 | 0 |
T9 | 19310 | 280 | 0 | 0 |
T10 | 9216 | 140 | 0 | 0 |
T11 | 13257 | 280 | 0 | 0 |
T12 | 13559 | 240 | 0 | 0 |
T13 | 98351 | 229 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 551205 | 0 | 0 |
T1 | 15911 | 20 | 0 | 0 |
T2 | 12450 | 140 | 0 | 0 |
T3 | 19608 | 200 | 0 | 0 |
T4 | 111926 | 146 | 0 | 0 |
T5 | 166439 | 407 | 0 | 0 |
T9 | 19310 | 280 | 0 | 0 |
T10 | 9216 | 140 | 0 | 0 |
T11 | 13257 | 280 | 0 | 0 |
T12 | 13559 | 240 | 0 | 0 |
T13 | 98351 | 229 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 18 | 18 | 100.00 |
Logical | 18 | 18 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T2,T3,T9 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Covered | T1,T2,T3 | |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 415724641 | 205477 | 0 | 0 |
DepthKnown_A | 415724641 | 414852436 | 0 | 0 |
RvalidKnown_A | 415724641 | 414852436 | 0 | 0 |
WreadyKnown_A | 415724641 | 414852436 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 415724641 | 205477 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 205477 | 0 | 0 |
T1 | 15911 | 2 | 0 | 0 |
T2 | 12450 | 70 | 0 | 0 |
T3 | 19608 | 82 | 0 | 0 |
T4 | 111926 | 120 | 0 | 0 |
T5 | 166439 | 409 | 0 | 0 |
T9 | 19310 | 122 | 0 | 0 |
T10 | 9216 | 14 | 0 | 0 |
T11 | 13257 | 107 | 0 | 0 |
T12 | 13559 | 107 | 0 | 0 |
T13 | 98351 | 158 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 414852436 | 0 | 0 |
T1 | 15911 | 15668 | 0 | 0 |
T2 | 12450 | 12163 | 0 | 0 |
T3 | 19608 | 19347 | 0 | 0 |
T4 | 111926 | 110835 | 0 | 0 |
T5 | 166439 | 165010 | 0 | 0 |
T9 | 19310 | 19040 | 0 | 0 |
T10 | 9216 | 8988 | 0 | 0 |
T11 | 13257 | 12981 | 0 | 0 |
T12 | 13559 | 13253 | 0 | 0 |
T13 | 98351 | 97030 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 415724641 | 205477 | 0 | 0 |
T1 | 15911 | 2 | 0 | 0 |
T2 | 12450 | 70 | 0 | 0 |
T3 | 19608 | 82 | 0 | 0 |
T4 | 111926 | 120 | 0 | 0 |
T5 | 166439 | 409 | 0 | 0 |
T9 | 19310 | 122 | 0 | 0 |
T10 | 9216 | 14 | 0 | 0 |
T11 | 13257 | 107 | 0 | 0 |
T12 | 13559 | 107 | 0 | 0 |
T13 | 98351 | 158 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |