SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 69.44 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
buf_err_code_cg_wrap[OtpSecret0ErrIdx] | 0.00 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
fsm_err | 0 | 1 | 1 | |
check_fail | 0 | 1 | 1 | |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 | |
no_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119150 | 1 | T3 | 1 | T12 | 91 | T13 | 144 | ||||
check_fail | 3 | 1 | T65 | 1 | T66 | 1 | T67 | 1 | ||||
ecc_uncorr_err | 279 | 1 | T50 | 69 | T129 | 1 | T132 | 46 | ||||
ecc_corr_err | 75 | 1 | T63 | 19 | T64 | 56 | - | - | ||||
no_err | 154394 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119408 | 1 | T12 | 91 | T13 | 144 | T14 | 1 | ||||
check_fail | 1 | 1 | T42 | 1 | - | - | - | - | ||||
ecc_uncorr_err | 25 | 1 | T28 | 1 | T137 | 1 | T82 | 21 | ||||
ecc_corr_err | 26 | 1 | T39 | 13 | T40 | 2 | T41 | 11 | ||||
no_err | 154361 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119214 | 1 | T3 | 1 | T12 | 91 | T13 | 144 | ||||
check_fail | 12 | 1 | T32 | 1 | T33 | 1 | T34 | 1 | ||||
ecc_uncorr_err | 234 | 1 | T70 | 1 | T71 | 1 | T35 | 1 | ||||
ecc_corr_err | 168 | 1 | T29 | 78 | T30 | 48 | T31 | 42 | ||||
no_err | 154544 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119352 | 1 | T3 | 1 | T12 | 91 | T13 | 144 | ||||
check_fail | 19 | 1 | T14 | 1 | T45 | 1 | T46 | 1 | ||||
ecc_uncorr_err | 69 | 1 | T83 | 1 | T117 | 1 | T118 | 1 | ||||
ecc_corr_err | 131 | 1 | T44 | 131 | - | - | - | - | ||||
no_err | 154503 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119265 | 1 | T3 | 1 | T12 | 91 | T13 | 144 | ||||
check_fail | 18 | 1 | T52 | 1 | T53 | 1 | T54 | 1 | ||||
ecc_uncorr_err | 153 | 1 | T26 | 1 | T74 | 55 | T81 | 1 | ||||
ecc_corr_err | 203 | 1 | T50 | 65 | T51 | 138 | - | - | ||||
no_err | 154339 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |