SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
85.71 | 80.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] | 57.14 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
57.14 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 3 | 4 | 57.14 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 3 | 4 | 57.14 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 3 | 4 | 57.14 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119291 | 1 | T12 | 91 | T13 | 144 | T77 | 34 | ||||
check_fail | 2 | 1 | T145 | 1 | T144 | 1 | - | - | ||||
access_err | 52771 | 1 | T1 | 4 | T6 | 8 | T10 | 11 | ||||
no_err | 102383 | 1 | T1 | 73 | T4 | 55 | T6 | 49 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119055 | 1 | T12 | 91 | T13 | 144 | T77 | 34 | ||||
check_fail | 5 | 1 | T78 | 1 | T145 | 1 | T147 | 1 | ||||
access_err | 52485 | 1 | T10 | 14 | T11 | 24 | T17 | 240 | ||||
ecc_uncorr_err | 348 | 1 | T116 | 1 | T96 | 1 | T99 | 1 | ||||
ecc_corr_err | 1010 | 1 | T142 | 1 | T75 | 98 | T146 | 8 | ||||
no_err | 101570 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118985 | 1 | T12 | 91 | T13 | 144 | T77 | 34 | ||||
check_fail | 2 | 1 | T78 | 1 | T145 | 1 | - | - | ||||
access_err | 52201 | 1 | T10 | 4 | T11 | 71 | T12 | 16 | ||||
ecc_uncorr_err | 428 | 1 | T94 | 1 | T172 | 1 | T174 | 1 | ||||
ecc_corr_err | 951 | 1 | T89 | 58 | T74 | 47 | T146 | 1 | ||||
no_err | 101819 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119155 | 1 | T12 | 91 | T13 | 144 | T77 | 34 | ||||
check_fail | 3 | 1 | T78 | 1 | T143 | 1 | T144 | 1 | ||||
access_err | 52897 | 1 | T4 | 5 | T6 | 4 | T10 | 12 | ||||
ecc_uncorr_err | 252 | 1 | T3 | 1 | T150 | 1 | T202 | 1 | ||||
ecc_corr_err | 678 | 1 | T142 | 3 | T89 | 12 | T74 | 88 | ||||
no_err | 101314 | 1 | T1 | 77 | T4 | 50 | T6 | 53 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 119128 | 1 | T12 | 91 | T13 | 144 | T77 | 34 | ||||
check_fail | 4 | 1 | T78 | 1 | T145 | 1 | T147 | 1 | ||||
access_err | 51316 | 1 | T10 | 11 | T11 | 74 | T17 | 187 | ||||
ecc_uncorr_err | 296 | 1 | T208 | 1 | T209 | 1 | T146 | 21 | ||||
ecc_corr_err | 1120 | 1 | T142 | 2 | T149 | 3 | T146 | 5 | ||||
no_err | 102358 | 1 | T1 | 77 | T4 | 55 | T6 | 57 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |