SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20020714 | 1 | T1 | 5006 | T2 | 49 | T3 | 967 | ||||
auto[1] | 11535793 | 1 | T1 | 13 | T3 | 13 | T4 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 31556295 | 1 | T1 | 5019 | T2 | 49 | T3 | 980 | ||||
values[1] | 28 | 1 | T276 | 3 | T277 | 2 | T278 | 1 | ||||
values[2] | 1 | 1 | T284 | 1 | - | - | - | - | ||||
values[3] | 108 | 1 | T276 | 1 | T277 | 7 | T278 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 31556294 | 1 | T1 | 5019 | T2 | 49 | T3 | 980 | ||||
values[1] | 20 | 1 | T277 | 2 | T278 | 1 | T284 | 2 | ||||
values[2] | 8 | 1 | T276 | 1 | T284 | 1 | T352 | 1 | ||||
values[3] | 121 | 1 | T276 | 3 | T277 | 8 | T278 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 31556187 | 1 | T1 | 5019 | T2 | 49 | T3 | 980 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T276 | 4 | T277 | 6 | T278 | 3 | ||||
auto[TlIntgErrData] | 108 | 1 | T276 | 3 | T277 | 7 | T278 | 5 | ||||
auto[TlIntgErrBoth] | 105 | 1 | T276 | 3 | T277 | 7 | T278 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 2811626 | 0 | T11 | 70 | T17 | 22 | T18 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2811409 | 1 | T11 | 70 | T17 | 22 | T18 | 64 | ||||
values[1] | 21 | 1 | T276 | 1 | T277 | 1 | T284 | 3 | ||||
values[2] | 6 | 1 | T352 | 2 | T353 | 1 | T354 | 1 | ||||
values[3] | 105 | 1 | T276 | 5 | T277 | 3 | T278 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2811407 | 1 | T11 | 70 | T17 | 22 | T18 | 64 | ||||
values[1] | 29 | 1 | T276 | 1 | T277 | 3 | T278 | 1 | ||||
values[2] | 8 | 1 | T355 | 1 | T353 | 1 | T356 | 4 | ||||
values[3] | 91 | 1 | T276 | 4 | T277 | 5 | T278 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 2811306 | 1 | T11 | 70 | T17 | 22 | T18 | 64 | ||||
auto[TlIntgErrCmd] | 101 | 1 | T276 | 4 | T277 | 6 | T278 | 5 | ||||
auto[TlIntgErrData] | 103 | 1 | T276 | 2 | T277 | 9 | T278 | 3 | ||||
auto[TlIntgErrBoth] | 116 | 1 | T276 | 4 | T277 | 5 | T278 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |