Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23706526

1

T1

4196

T2

43

T3

789

full_word

7849981

1

T1

823

T2

6

T3

191

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31556187	1			T1	5019		T2	49		T3	980
auto[TlIntgErrCmd]	107	1			T276	4		T277	6		T278	3
auto[TlIntgErrData]	108	1			T276	3		T277	7		T278	5
auto[TlIntgErrBoth]	105	1			T276	3		T277	7		T278	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9529782

1

T1

4746

T2

1

T3

769

auto[1]

22026725

1

T1

273

T2

48

T3

211

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6046606	1			T1	4037		T3	674		T4	4364
auto[TlIntgErrNone]	partial	auto[1]	17659626	1			T1	159		T2	43		T3	115
auto[TlIntgErrNone]	full_word	auto[0]	3483028	1			T1	709		T2	1		T3	95
auto[TlIntgErrNone]	full_word	auto[1]	4366927	1			T1	114		T2	5		T3	96
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T276	2		T277	2		T278	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T276	1		T277	3		T284	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T277	1		T355	1		T353	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T276	1		T284	1		T357	2
auto[TlIntgErrData]	partial	auto[0]	54	1			T276	2		T277	4		T278	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T276	1		T277	3		T278	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T284	1		T358	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T355	1		T353	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T276	1		T277	2		T284	5
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T276	2		T277	5		T278	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T284	1		T357	1		T360	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T353	2		T354	1		T356	1