Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	452459364	7423195	0	0
check_regwen_rd_A	452459364	2607	0	0
check_timeout_rd_A	452459364	1257	0	0
check_trigger_regwen_rd_A	452459364	2531	0	0
consistency_check_period_rd_A	452459364	2476	0	0
creator_sw_cfg_read_lock_rd_A	452459364	1207	0	0
direct_access_address_rd_A	452459364	1045	0	0
direct_access_wdata_0_rd_A	452459364	542	0	0
direct_access_wdata_1_rd_A	452459364	771	0	0
integrity_check_period_rd_A	452459364	2496	0	0
intr_enable_rd_A	452459364	3188	0	0
owner_sw_cfg_read_lock_rd_A	452459364	1131	0	0
rot_creator_auth_codesign_read_lock_rd_A	452459364	1442	0	0
rot_creator_auth_state_read_lock_rd_A	452459364	1065	0	0
vendor_test_read_lock_rd_A	452459364	1164	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	7423195	0	0
T7	442742	104107	0	0
T8	255763	47367	0	0
T9	315073	92718	0	0
T15	0	98453	0	0
T19	0	103649	0	0
T20	0	235586	0	0
T26	9683	0	0	0
T38	0	70528	0	0
T72	0	84196	0	0
T101	68739	0	0	0
T109	78130	0	0	0
T110	10299	0	0	0
T120	0	172654	0	0
T215	0	40173	0	0
T236	95821	0	0	0
T240	8292	0	0	0
T285	31094	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	2607	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	48	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	103	0	0
T275	19474	0	0	0
T293	0	135	0	0
T294	0	92	0	0
T295	0	148	0	0
T304	15506	0	0	0
T331	0	89	0	0
T332	0	39	0	0
T333	0	52	0	0
T334	0	26	0	0
T335	0	39	0	0
T336	4739	0	0	0
T337	25313	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1257	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	42	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	58	0	0
T275	19474	0	0	0
T293	0	109	0	0
T294	0	96	0	0
T295	0	183	0	0
T304	15506	0	0	0
T331	0	67	0	0
T332	0	67	0	0
T333	0	88	0	0
T334	0	22	0	0
T335	0	30	0	0
T336	4739	0	0	0
T337	25313	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	2531	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	55	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	73	0	0
T275	19474	0	0	0
T293	0	161	0	0
T294	0	61	0	0
T295	0	151	0	0
T304	15506	0	0	0
T331	0	80	0	0
T332	0	31	0	0
T333	0	61	0	0
T334	0	43	0	0
T335	0	51	0	0
T336	4739	0	0	0
T337	25313	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	2476	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	57	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	104	0	0
T275	19474	0	0	0
T293	0	135	0	0
T294	0	69	0	0
T295	0	158	0	0
T304	15506	0	0	0
T331	0	64	0	0
T332	0	55	0	0
T333	0	59	0	0
T334	0	29	0	0
T335	0	81	0	0
T336	4739	0	0	0
T337	25313	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1207	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	62	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	64	0	0
T275	19474	0	0	0
T293	0	118	0	0
T294	0	76	0	0
T295	0	194	0	0
T304	15506	0	0	0
T331	0	92	0	0
T332	0	49	0	0
T333	0	25	0	0
T334	0	35	0	0
T335	0	57	0	0
T336	4739	0	0	0
T337	25313	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1045	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	27	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	46	0	0
T275	19474	0	0	0
T293	0	140	0	0
T294	0	87	0	0
T295	0	158	0	0
T304	15506	0	0	0
T331	0	101	0	0
T332	0	32	0	0
T333	0	28	0	0
T334	0	34	0	0
T335	0	58	0	0
T336	4739	0	0	0
T337	25313	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	542	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	22	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	38	0	0
T275	19474	0	0	0
T293	0	80	0	0
T294	0	38	0	0
T295	0	72	0	0
T304	15506	0	0	0
T331	0	49	0	0
T332	0	18	0	0
T333	0	5	0	0
T334	0	13	0	0
T335	0	18	0	0
T336	4739	0	0	0
T337	25313	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	771	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	37	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	91	0	0
T275	19474	0	0	0
T293	0	73	0	0
T294	0	42	0	0
T295	0	161	0	0
T304	15506	0	0	0
T331	0	65	0	0
T332	0	23	0	0
T333	0	12	0	0
T334	0	6	0	0
T335	0	42	0	0
T336	4739	0	0	0
T337	25313	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	2496	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	45	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	82	0	0
T275	19474	0	0	0
T293	0	96	0	0
T294	0	65	0	0
T295	0	143	0	0
T304	15506	0	0	0
T331	0	89	0	0
T332	0	34	0	0
T333	0	60	0	0
T334	0	59	0	0
T335	0	68	0	0
T336	4739	0	0	0
T337	25313	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	3188	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	48	0	0
T192	16458	0	0	0
T227	0	11	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	96	0	0
T275	19474	0	0	0
T293	0	139	0	0
T294	0	92	0	0
T304	15506	0	0	0
T331	0	114	0	0
T332	0	48	0	0
T336	4739	0	0	0
T337	25313	0	0	0
T338	0	1	0	0
T339	0	11	0	0
T340	0	14	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1131	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	38	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	82	0	0
T275	19474	0	0	0
T293	0	134	0	0
T294	0	66	0	0
T295	0	153	0	0
T304	15506	0	0	0
T331	0	57	0	0
T332	0	30	0	0
T333	0	40	0	0
T334	0	28	0	0
T335	0	43	0	0
T336	4739	0	0	0
T337	25313	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1442	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	93	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	110	0	0
T275	19474	0	0	0
T293	0	110	0	0
T294	0	108	0	0
T295	0	187	0	0
T304	15506	0	0	0
T331	0	77	0	0
T332	0	55	0	0
T333	0	59	0	0
T334	0	25	0	0
T335	0	97	0	0
T336	4739	0	0	0
T337	25313	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1065	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	40	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	73	0	0
T275	19474	0	0	0
T293	0	125	0	0
T294	0	36	0	0
T295	0	126	0	0
T304	15506	0	0	0
T331	0	98	0	0
T332	0	42	0	0
T333	0	21	0	0
T334	0	59	0	0
T335	0	56	0	0
T336	4739	0	0	0
T337	25313	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452459364	1164	0	0
T39	88978	0	0	0
T137	14132	0	0	0
T154	0	70	0	0
T192	16458	0	0	0
T235	146132	0	0	0
T262	105262	0	0	0
T263	372199	55	0	0
T275	19474	0	0	0
T293	0	72	0	0
T294	0	62	0	0
T295	0	110	0	0
T304	15506	0	0	0
T331	0	82	0	0
T332	0	47	0	0
T333	0	42	0	0
T334	0	48	0	0
T335	0	55	0	0
T336	4739	0	0	0
T337	25313	0	0	0