Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 86 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
ALWAYS | 153 | 3 | 3 | 100.00 |
ALWAYS | 164 | 61 | 61 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
224 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
225 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
276 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
277 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
279 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
339 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
Conditions | 29 | 29 | 100.00 |
Logical | 29 | 29 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T3,T4 |
1 | Excluded | |
VC_COV_UNR |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T23,T24,T25 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T145,T144 |
1 | Covered | T145,T144 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T3,T12,T13 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T10 |
1 | 1 | Covered | T1,T3,T4 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
13 |
11 |
84.62 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T3,T12,T13 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T1,T3,T4 |
ReadWaitSt |
252 |
Covered |
T1,T3,T4 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->ErrorSt |
315 |
Covered |
T3,T12,T13 |
|
IdleSt->ReadSt |
236 |
Covered |
T1,T3,T4 |
|
InitSt->ErrorSt |
315 |
Covered |
T191,T192,T193 |
|
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
InitWaitSt->ErrorSt |
224 |
Covered |
T189,T194,T195 |
|
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
ReadSt->ErrorSt |
315 |
Not Covered |
|
|
ReadSt->IdleSt |
255 |
Covered |
T1,T6,T10 |
|
ReadSt->ReadWaitSt |
252 |
Covered |
T1,T3,T4 |
|
ReadWaitSt->ErrorSt |
276 |
Not Covered |
|
|
ReadWaitSt->IdleSt |
270 |
Covered |
T1,T3,T4 |
|
ResetSt->ErrorSt |
315 |
Covered |
T77,T78,T79 |
|
ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
7 |
7 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests | Exclude Annotation |
AccessError |
256 |
Covered |
T1,T6,T10 |
|
CheckFailError |
317 |
Covered |
T145,T144 |
|
FsmStateError |
289 |
Covered |
T3,T12,T13 |
|
MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
NoError |
235 |
Covered |
T1,T2,T3 |
|
transitions | Line No. | Covered | Tests | Exclude Annotation |
AccessError->CheckFailError |
317 |
Excluded |
|
|
AccessError->FsmStateError |
325 |
Covered |
T113,T7,T8 |
|
AccessError->MacroEccCorrError |
221 |
Excluded |
|
|
AccessError->NoError |
235 |
Covered |
T1,T6,T10 |
|
CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
|
CheckFailError->NoError |
235 |
Covered |
T145,T144 |
|
FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
|
FsmStateError->NoError |
235 |
Covered |
T3,T12,T13 |
|
MacroEccCorrError->AccessError |
256 |
Excluded |
|
|
MacroEccCorrError->CheckFailError |
317 |
Excluded |
|
|
MacroEccCorrError->FsmStateError |
325 |
Excluded |
|
|
MacroEccCorrError->NoError |
235 |
Excluded |
|
|
NoError->AccessError |
256 |
Covered |
T1,T6,T10 |
|
NoError->CheckFailError |
317 |
Covered |
T145,T144 |
|
NoError->FsmStateError |
289 |
Covered |
T3,T12,T13 |
|
NoError->MacroEccCorrError |
221 |
Excluded |
|
|
Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
Branches |
|
41 |
41 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
18 |
18 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
IF |
153 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests | Exclude Annotation |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
|
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
|
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T17,T15 |
|
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T6,T10 |
|
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T1,T3,T4 |
|
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T23,T24,T25 |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T3,T12,T13 |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T12,T13,T77 |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T12,T13,T77 |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T3,T12,T13 |
|
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
|
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T145,T144 |
1 |
0 |
Covered |
T145,T144 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T12,T13 |
1 |
0 |
Covered |
T3,T12,T13 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 153 if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T69,T116 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
7032 |
0 |
0 |
T125 |
8152 |
0 |
0 |
0 |
T144 |
0 |
3444 |
0 |
0 |
T145 |
10221 |
3588 |
0 |
0 |
T161 |
199855 |
0 |
0 |
0 |
T162 |
15730 |
0 |
0 |
0 |
T163 |
16568 |
0 |
0 |
0 |
T164 |
13717 |
0 |
0 |
0 |
T165 |
15530 |
0 |
0 |
0 |
T166 |
50904 |
0 |
0 |
0 |
T167 |
95022 |
0 |
0 |
0 |
T168 |
11821 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100201986 |
0 |
0 |
T1 |
88960 |
9788 |
0 |
0 |
T2 |
4794 |
72 |
0 |
0 |
T3 |
9129 |
3816 |
0 |
0 |
T4 |
33829 |
1750 |
0 |
0 |
T6 |
34875 |
6597 |
0 |
0 |
T10 |
37907 |
561 |
0 |
0 |
T11 |
62636 |
484 |
0 |
0 |
T12 |
30780 |
15395 |
0 |
0 |
T13 |
18089 |
5743 |
0 |
0 |
T14 |
14793 |
3809 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100201986 |
0 |
0 |
T1 |
88960 |
9788 |
0 |
0 |
T2 |
4794 |
72 |
0 |
0 |
T3 |
9129 |
3816 |
0 |
0 |
T4 |
33829 |
1750 |
0 |
0 |
T6 |
34875 |
6597 |
0 |
0 |
T10 |
37907 |
561 |
0 |
0 |
T11 |
62636 |
484 |
0 |
0 |
T12 |
30780 |
15395 |
0 |
0 |
T13 |
18089 |
5743 |
0 |
0 |
T14 |
14793 |
3809 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
0 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
191726353 |
0 |
0 |
T1 |
88960 |
880 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
2741 |
0 |
0 |
T6 |
34875 |
2668 |
0 |
0 |
T10 |
37907 |
3084 |
0 |
0 |
T11 |
62636 |
19205 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
706 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
91484 |
0 |
0 |
T18 |
0 |
8349 |
0 |
0 |
T77 |
0 |
1644 |
0 |
0 |
T108 |
0 |
1090 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
7765 |
0 |
0 |
T1 |
88960 |
1 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
0 |
0 |
0 |
T6 |
34875 |
1 |
0 |
0 |
T10 |
37907 |
2 |
0 |
0 |
T11 |
62636 |
3 |
0 |
0 |
T12 |
30780 |
3 |
0 |
0 |
T13 |
18089 |
4 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
25 |
0 |
0 |
T18 |
0 |
7 |
0 |
0 |
T69 |
0 |
8 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
2038361 |
0 |
0 |
T1 |
88960 |
4751 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
0 |
0 |
0 |
T6 |
34875 |
0 |
0 |
0 |
T10 |
37907 |
1124 |
0 |
0 |
T11 |
62636 |
0 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
0 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T16 |
0 |
8785 |
0 |
0 |
T17 |
0 |
26802 |
0 |
0 |
T18 |
0 |
3162 |
0 |
0 |
T100 |
0 |
5574 |
0 |
0 |
T101 |
0 |
5473 |
0 |
0 |
T103 |
0 |
18020 |
0 |
0 |
T104 |
0 |
11945 |
0 |
0 |
T109 |
0 |
10015 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
25899736 |
0 |
0 |
T1 |
88960 |
71128 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
9702 |
0 |
0 |
T6 |
34875 |
18417 |
0 |
0 |
T10 |
37907 |
31673 |
0 |
0 |
T11 |
62636 |
51093 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
12530 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
327938 |
0 |
0 |
T18 |
0 |
46822 |
0 |
0 |
T77 |
0 |
2479 |
0 |
0 |
T108 |
0 |
6608 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T94,T83,T87 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T142,T75,T146 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T23,T24,T25 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T78,T145,T147 |
1 | Covered | T78,T145,T147 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T3,T12,T13 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T1,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T3,T6 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
13 |
12 |
92.31 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T3,T12,T13 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T1,T3,T6 |
ReadWaitSt |
252 |
Covered |
T1,T3,T6 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->ErrorSt |
315 |
Covered |
T3,T12,T13 |
|
IdleSt->ReadSt |
236 |
Covered |
T1,T3,T6 |
|
InitSt->ErrorSt |
315 |
Covered |
T191,T189,T194 |
|
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
InitWaitSt->ErrorSt |
224 |
Covered |
T116,T96,T99 |
|
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
ReadSt->ErrorSt |
315 |
Not Covered |
|
|
ReadSt->IdleSt |
255 |
Covered |
T10,T11,T17 |
|
ReadSt->ReadWaitSt |
252 |
Covered |
T1,T3,T6 |
|
ReadWaitSt->ErrorSt |
276 |
Covered |
T146,T196,T197 |
|
ReadWaitSt->IdleSt |
270 |
Covered |
T1,T3,T6 |
|
ResetSt->ErrorSt |
315 |
Covered |
T77,T78,T79 |
|
ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
11 |
10 |
90.91 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
AccessError |
256 |
Covered |
T10,T11,T17 |
CheckFailError |
317 |
Covered |
T78,T145,T147 |
FsmStateError |
289 |
Covered |
T3,T12,T13 |
MacroEccCorrError |
221 |
Covered |
T94,T83,T142 |
NoError |
235 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
AccessError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
AccessError->FsmStateError |
325 |
Covered |
T113,T153,T7 |
|
AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
AccessError->NoError |
235 |
Covered |
T10,T11,T17 |
|
CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
CheckFailError->NoError |
235 |
Covered |
T78,T145,T147 |
|
FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
FsmStateError->NoError |
235 |
Covered |
T3,T12,T13 |
|
MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
|
MacroEccCorrError->FsmStateError |
325 |
Covered |
T94,T83,T142 |
|
MacroEccCorrError->NoError |
235 |
Covered |
T75,T198,T50 |
|
NoError->AccessError |
256 |
Covered |
T10,T11,T17 |
|
NoError->CheckFailError |
317 |
Covered |
T78,T145,T147 |
|
NoError->FsmStateError |
289 |
Covered |
T3,T12,T13 |
|
NoError->MacroEccCorrError |
221 |
Covered |
T94,T83,T142 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
Branches |
|
44 |
44 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
23 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T94,T83,T87 |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T116,T96,T99 |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T17,T101 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T11,T17 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T142,T75,T146 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T1,T3,T6 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T146,T196,T197 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T23,T24,T25 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T3,T12,T13 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T12,T13,T77 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T12,T13,T77 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T3,T12,T13 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T78,T145,T147 |
1 |
0 |
Covered |
T78,T145,T147 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T12,T13 |
1 |
0 |
Covered |
T3,T12,T13 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
15461 |
0 |
0 |
T21 |
600091 |
0 |
0 |
0 |
T50 |
157050 |
0 |
0 |
0 |
T78 |
9400 |
2185 |
0 |
0 |
T143 |
0 |
3412 |
0 |
0 |
T144 |
0 |
3444 |
0 |
0 |
T145 |
0 |
3588 |
0 |
0 |
T147 |
0 |
2832 |
0 |
0 |
T154 |
166002 |
0 |
0 |
0 |
T155 |
9364 |
0 |
0 |
0 |
T156 |
18176 |
0 |
0 |
0 |
T157 |
9172 |
0 |
0 |
0 |
T158 |
10974 |
0 |
0 |
0 |
T159 |
54113 |
0 |
0 |
0 |
T160 |
12072 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100383099 |
0 |
0 |
T1 |
88960 |
10026 |
0 |
0 |
T2 |
4794 |
89 |
0 |
0 |
T3 |
9129 |
3850 |
0 |
0 |
T4 |
33829 |
1903 |
0 |
0 |
T6 |
34875 |
6648 |
0 |
0 |
T10 |
37907 |
680 |
0 |
0 |
T11 |
62636 |
637 |
0 |
0 |
T12 |
30780 |
15429 |
0 |
0 |
T13 |
18089 |
5811 |
0 |
0 |
T14 |
14793 |
3843 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100383099 |
0 |
0 |
T1 |
88960 |
10026 |
0 |
0 |
T2 |
4794 |
89 |
0 |
0 |
T3 |
9129 |
3850 |
0 |
0 |
T4 |
33829 |
1903 |
0 |
0 |
T6 |
34875 |
6648 |
0 |
0 |
T10 |
37907 |
680 |
0 |
0 |
T11 |
62636 |
637 |
0 |
0 |
T12 |
30780 |
15429 |
0 |
0 |
T13 |
18089 |
5811 |
0 |
0 |
T14 |
14793 |
3843 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
75 |
0 |
0 |
T7 |
442742 |
0 |
0 |
0 |
T8 |
255763 |
0 |
0 |
0 |
T70 |
9253 |
0 |
0 |
0 |
T71 |
15143 |
0 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T100 |
128769 |
0 |
0 |
0 |
T113 |
28802 |
0 |
0 |
0 |
T116 |
9980 |
1 |
0 |
0 |
T153 |
69010 |
0 |
0 |
0 |
T169 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T173 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
T176 |
0 |
1 |
0 |
0 |
T177 |
0 |
1 |
0 |
0 |
T184 |
15319 |
0 |
0 |
0 |
T185 |
96853 |
0 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
194476050 |
0 |
0 |
T1 |
88960 |
5998 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
1697 |
0 |
0 |
T6 |
34875 |
0 |
0 |
0 |
T10 |
37907 |
2335 |
0 |
0 |
T11 |
62636 |
18704 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
1984 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
87367 |
0 |
0 |
T18 |
0 |
10723 |
0 |
0 |
T77 |
0 |
1642 |
0 |
0 |
T100 |
0 |
11323 |
0 |
0 |
T108 |
0 |
1088 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
8248 |
0 |
0 |
T10 |
37907 |
9 |
0 |
0 |
T11 |
62636 |
3 |
0 |
0 |
T12 |
30780 |
4 |
0 |
0 |
T13 |
18089 |
6 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
666522 |
28 |
0 |
0 |
T18 |
73633 |
3 |
0 |
0 |
T69 |
48552 |
4 |
0 |
0 |
T77 |
10718 |
1 |
0 |
0 |
T100 |
0 |
3 |
0 |
0 |
T107 |
21695 |
0 |
0 |
0 |
T108 |
0 |
4 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
2295747 |
0 |
0 |
T1 |
88960 |
4486 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
0 |
0 |
0 |
T6 |
34875 |
0 |
0 |
0 |
T10 |
37907 |
0 |
0 |
0 |
T11 |
62636 |
0 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
0 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T16 |
0 |
10138 |
0 |
0 |
T17 |
0 |
53028 |
0 |
0 |
T95 |
0 |
2145 |
0 |
0 |
T97 |
0 |
1629 |
0 |
0 |
T100 |
0 |
11646 |
0 |
0 |
T102 |
0 |
181 |
0 |
0 |
T103 |
0 |
7838 |
0 |
0 |
T104 |
0 |
24676 |
0 |
0 |
T109 |
0 |
10015 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
26505500 |
0 |
0 |
T1 |
88960 |
70907 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
16625 |
0 |
0 |
T6 |
34875 |
18383 |
0 |
0 |
T10 |
37907 |
31571 |
0 |
0 |
T11 |
62636 |
50957 |
0 |
0 |
T12 |
30780 |
2623 |
0 |
0 |
T13 |
18089 |
12479 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
346293 |
0 |
0 |
T18 |
0 |
64331 |
0 |
0 |
T77 |
0 |
2462 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
Conditions | 34 | 33 | 97.06 |
Logical | 34 | 33 | 97.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T71,T26,T150 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T89,T74,T146 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T23,T24,T25 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T78,T145 |
1 | Covered | T78,T145 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T3,T12,T13 |
1 | Covered | T3,T12,T13 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T1,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111011000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T6 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T6,T10 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T6,T10 |
FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
13 |
12 |
92.31 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T3,T12,T13 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T1,T3,T6 |
ReadWaitSt |
252 |
Covered |
T1,T3,T6 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->ErrorSt |
315 |
Covered |
T3,T12,T13 |
|
IdleSt->ReadSt |
236 |
Covered |
T1,T3,T6 |
|
InitSt->ErrorSt |
315 |
Covered |
T191,T189,T194 |
|
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
InitWaitSt->ErrorSt |
224 |
Covered |
T108,T116,T94 |
|
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
ReadSt->ErrorSt |
315 |
Not Covered |
|
|
ReadSt->IdleSt |
255 |
Covered |
T10,T11,T12 |
|
ReadSt->ReadWaitSt |
252 |
Covered |
T1,T3,T6 |
|
ReadWaitSt->ErrorSt |
276 |
Covered |
T196,T199,T200 |
|
ReadWaitSt->IdleSt |
270 |
Covered |
T1,T3,T6 |
|
ResetSt->ErrorSt |
315 |
Covered |
T77,T78,T79 |
|
ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
11 |
10 |
90.91 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
AccessError |
256 |
Covered |
T10,T11,T12 |
CheckFailError |
317 |
Covered |
T78,T145 |
FsmStateError |
289 |
Covered |
T3,T12,T13 |
MacroEccCorrError |
221 |
Covered |
T71,T26,T150 |
NoError |
235 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
AccessError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
AccessError->FsmStateError |
325 |
Covered |
T12,T153,T7 |
|
AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
AccessError->NoError |
235 |
Covered |
T10,T11,T17 |
|
CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
CheckFailError->NoError |
235 |
Covered |
T78,T145 |
|
FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
FsmStateError->NoError |
235 |
Covered |
T3,T12,T13 |
|
MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
|
MacroEccCorrError->FsmStateError |
325 |
Covered |
T71,T26,T150 |
|
MacroEccCorrError->NoError |
235 |
Covered |
T89,T74,T198 |
|
NoError->AccessError |
256 |
Covered |
T10,T11,T12 |
|
NoError->CheckFailError |
317 |
Covered |
T78,T145 |
|
NoError->FsmStateError |
289 |
Covered |
T3,T13,T14 |
|
NoError->MacroEccCorrError |
221 |
Covered |
T71,T26,T150 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
Branches |
|
44 |
44 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
23 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T10 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T71,T26,T150 |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T94,T172,T174 |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T17,T8 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T11,T12 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T89,T74,T146 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T1,T3,T6 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T196,T199,T200 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T23,T24,T25 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T3,T12,T13 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T12,T13,T77 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T12,T13,T77 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T3,T12,T13 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T78,T145 |
1 |
0 |
Covered |
T78,T145 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T12,T13 |
1 |
0 |
Covered |
T3,T12,T13 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
5773 |
0 |
0 |
T21 |
600091 |
0 |
0 |
0 |
T50 |
157050 |
0 |
0 |
0 |
T78 |
9400 |
2185 |
0 |
0 |
T145 |
0 |
3588 |
0 |
0 |
T154 |
166002 |
0 |
0 |
0 |
T155 |
9364 |
0 |
0 |
0 |
T156 |
18176 |
0 |
0 |
0 |
T157 |
9172 |
0 |
0 |
0 |
T158 |
10974 |
0 |
0 |
0 |
T159 |
54113 |
0 |
0 |
0 |
T160 |
12072 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100562934 |
0 |
0 |
T1 |
88960 |
10264 |
0 |
0 |
T2 |
4794 |
106 |
0 |
0 |
T3 |
9129 |
3884 |
0 |
0 |
T4 |
33829 |
2056 |
0 |
0 |
T6 |
34875 |
6699 |
0 |
0 |
T10 |
37907 |
799 |
0 |
0 |
T11 |
62636 |
790 |
0 |
0 |
T12 |
30780 |
15463 |
0 |
0 |
T13 |
18089 |
5879 |
0 |
0 |
T14 |
14793 |
3877 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
100562934 |
0 |
0 |
T1 |
88960 |
10264 |
0 |
0 |
T2 |
4794 |
106 |
0 |
0 |
T3 |
9129 |
3884 |
0 |
0 |
T4 |
33829 |
2056 |
0 |
0 |
T6 |
34875 |
6699 |
0 |
0 |
T10 |
37907 |
799 |
0 |
0 |
T11 |
62636 |
790 |
0 |
0 |
T12 |
30780 |
15463 |
0 |
0 |
T13 |
18089 |
5879 |
0 |
0 |
T14 |
14793 |
3877 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
55 |
0 |
0 |
T15 |
571479 |
0 |
0 |
0 |
T16 |
605625 |
0 |
0 |
0 |
T83 |
19111 |
0 |
0 |
0 |
T94 |
12217 |
1 |
0 |
0 |
T95 |
25725 |
0 |
0 |
0 |
T96 |
11848 |
0 |
0 |
0 |
T97 |
18415 |
0 |
0 |
0 |
T98 |
48348 |
0 |
0 |
0 |
T99 |
7474 |
0 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T172 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T178 |
0 |
1 |
0 |
0 |
T179 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
T181 |
0 |
1 |
0 |
0 |
T182 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
T186 |
21573 |
0 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
195199152 |
0 |
0 |
T1 |
88960 |
4833 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
2136 |
0 |
0 |
T6 |
34875 |
2666 |
0 |
0 |
T10 |
37907 |
2047 |
0 |
0 |
T11 |
62636 |
24135 |
0 |
0 |
T12 |
30780 |
21043 |
0 |
0 |
T13 |
18089 |
1980 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
80634 |
0 |
0 |
T18 |
0 |
11497 |
0 |
0 |
T77 |
0 |
1640 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1144 |
1144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
8331 |
0 |
0 |
T10 |
37907 |
4 |
0 |
0 |
T11 |
62636 |
6 |
0 |
0 |
T12 |
30780 |
3 |
0 |
0 |
T13 |
18089 |
5 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
666522 |
30 |
0 |
0 |
T18 |
73633 |
2 |
0 |
0 |
T69 |
48552 |
6 |
0 |
0 |
T77 |
10718 |
2 |
0 |
0 |
T100 |
0 |
2 |
0 |
0 |
T107 |
21695 |
0 |
0 |
0 |
T108 |
0 |
2 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
1742756 |
0 |
0 |
T11 |
62636 |
7558 |
0 |
0 |
T12 |
30780 |
0 |
0 |
0 |
T13 |
18089 |
0 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T16 |
0 |
738 |
0 |
0 |
T17 |
666522 |
13028 |
0 |
0 |
T18 |
73633 |
0 |
0 |
0 |
T69 |
48552 |
0 |
0 |
0 |
T77 |
10718 |
0 |
0 |
0 |
T98 |
0 |
4297 |
0 |
0 |
T100 |
0 |
16763 |
0 |
0 |
T101 |
0 |
2376 |
0 |
0 |
T103 |
0 |
15547 |
0 |
0 |
T104 |
0 |
36705 |
0 |
0 |
T106 |
0 |
4365 |
0 |
0 |
T107 |
21695 |
0 |
0 |
0 |
T108 |
11796 |
0 |
0 |
0 |
T188 |
0 |
5024 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
19505193 |
0 |
0 |
T1 |
88960 |
70686 |
0 |
0 |
T2 |
4794 |
0 |
0 |
0 |
T3 |
9129 |
0 |
0 |
0 |
T4 |
33829 |
0 |
0 |
0 |
T6 |
34875 |
18349 |
0 |
0 |
T10 |
37907 |
31469 |
0 |
0 |
T11 |
62636 |
50821 |
0 |
0 |
T12 |
30780 |
2606 |
0 |
0 |
T13 |
18089 |
12428 |
0 |
0 |
T14 |
14793 |
0 |
0 |
0 |
T17 |
0 |
306500 |
0 |
0 |
T18 |
0 |
64127 |
0 |
0 |
T100 |
0 |
106496 |
0 |
0 |
T108 |
0 |
6540 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449476454 |
448616310 |
0 |
0 |
T1 |
88960 |
87726 |
0 |
0 |
T2 |
4794 |
4736 |
0 |
0 |
T3 |
9129 |
8872 |
0 |
0 |
T4 |
33829 |
33144 |
0 |
0 |
T6 |
34875 |
34490 |
0 |
0 |
T10 |
37907 |
37051 |
0 |
0 |
T11 |
62636 |
61944 |
0 |
0 |
T12 |
30780 |
30524 |
0 |
0 |
T13 |
18089 |
17702 |
0 |
0 |
T14 |
14793 |
14558 |
0 |
0 |