Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T28,T87

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T142,T89,T74

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T143,T144
1	Covered	T78,T143,T144

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T12,T13,T14

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T10
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T12,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T12,T13,T14
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T108,T116,T96
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T150,T94
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T6,T10
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T151,T152,T201
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T6,T10
CheckFailError	317	Covered	T78,T143,T144
FsmStateError	289	Covered	T12,T13,T14
MacroEccCorrError	221	Covered	T26,T28,T142
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T113,T153,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T6,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T143,T144
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T12,T13,T14
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T26,T28,T142
MacroEccCorrError->NoError	235	Covered	T89,T74,T75
NoError->AccessError	256	Covered	T4,T6,T10
NoError->CheckFailError	317	Covered	T78,T143,T144
NoError->FsmStateError	289	Covered	T12,T13,T14
NoError->MacroEccCorrError	221	Covered	T26,T28,T142

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T26,T28,T87
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T150,T202
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T17,T8
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T142,T89,T74
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T151,T152,T201
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T12,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T13,T69
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T13,T69
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T143,T144
1	0	Covered	T78,T143,T144
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12,T13,T14
1	0	Covered	T3,T12,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449476454	448616310	0	0
DigestKnown_A	449476454	448616310	0	0
DigestOffsetMustBeRepresentable_A	1144	1144	0	0
EccErrorState_A	449476454	9041	0	0
ErrorKnown_A	449476454	448616310	0	0
FsmStateKnown_A	449476454	448616310	0	0
InitDoneKnown_A	449476454	448616310	0	0
InitReadLocksPartition_A	449476454	100741704	0	0
InitWriteLocksPartition_A	449476454	100741704	0	0
OffsetMustBeBlockAligned_A	1144	1144	0	0
OtpAddrKnown_A	449476454	448616310	0	0
OtpCmdKnown_A	449476454	448616310	0	0
OtpErrorState_A	449476454	45	0	0
OtpReqKnown_A	449476454	448616310	0	0
OtpSizeKnown_A	449476454	448616310	0	0
OtpWdataKnown_A	449476454	448616310	0	0
ReadLockPropagation_A	449476454	198345440	0	0
SizeMustBeBlockAligned_A	1144	1144	0	0
TlulGntKnown_A	449476454	448616310	0	0
TlulRdataKnown_A	449476454	448616310	0	0
TlulReadOnReadLock_A	449476454	8181	0	0
TlulRerrorKnown_A	449476454	448616310	0	0
TlulRvalidKnown_A	449476454	448616310	0	0
WriteLockPropagation_A	449476454	2050189	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449476454	25473211	0	0
u_state_regs_A	449476454	448616310	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	9041	0	0
T21	600091	0	0	0
T50	157050	0	0	0
T78	9400	2185	0	0
T143	0	3412	0	0
T144	0	3444	0	0
T154	166002	0	0	0
T155	9364	0	0	0
T156	18176	0	0	0
T157	9172	0	0	0
T158	10974	0	0	0
T159	54113	0	0	0
T160	12072	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	100741704	0	0
T1	88960	10502	0	0
T2	4794	123	0	0
T3	9129	3908	0	0
T4	33829	2209	0	0
T6	34875	6750	0	0
T10	37907	918	0	0
T11	62636	943	0	0
T12	30780	15497	0	0
T13	18089	5947	0	0
T14	14793	3911	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	100741704	0	0
T1	88960	10502	0	0
T2	4794	123	0	0
T3	9129	3908	0	0
T4	33829	2209	0	0
T6	34875	6750	0	0
T10	37907	918	0	0
T11	62636	943	0	0
T12	30780	15497	0	0
T13	18089	5947	0	0
T14	14793	3911	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	45	0	0
T3	9129	1	0	0
T4	33829	0	0	0
T6	34875	0	0	0
T10	37907	0	0	0
T11	62636	0	0	0
T12	30780	0	0	0
T13	18089	0	0	0
T14	14793	0	0	0
T17	666522	0	0	0
T107	21695	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	198345440	0	0
T1	88960	1857	0	0
T2	4794	0	0	0
T3	9129	0	0	0
T4	33829	1038	0	0
T6	34875	2659	0	0
T10	37907	2866	0	0
T11	62636	29237	0	0
T12	30780	21024	0	0
T13	18089	0	0	0
T14	14793	0	0	0
T17	0	82241	0	0
T18	0	8575	0	0
T77	0	1638	0	0
T108	0	1084	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	8181	0	0
T4	33829	1	0	0
T6	34875	2	0	0
T10	37907	5	0	0
T11	62636	4	0	0
T12	30780	3	0	0
T13	18089	4	0	0
T14	14793	0	0	0
T17	666522	30	0	0
T18	0	4	0	0
T69	0	5	0	0
T77	10718	0	0	0
T107	21695	0	0	0
T108	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	2050189	0	0
T1	88960	1012	0	0
T2	4794	0	0	0
T3	9129	0	0	0
T4	33829	0	0	0
T6	34875	0	0	0
T10	37907	0	0	0
T11	62636	0	0	0
T12	30780	0	0	0
T13	18089	0	0	0
T14	14793	0	0	0
T16	0	9144	0	0
T17	0	25227	0	0
T18	0	3162	0	0
T101	0	2366	0	0
T103	0	16176	0	0
T104	0	12731	0	0
T106	0	6866	0	0
T109	0	19519	0	0
T186	0	4903	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	25473211	0	0
T1	88960	11669	0	0
T2	4794	0	0	0
T3	9129	2392	0	0
T4	33829	16455	0	0
T6	34875	18315	0	0
T10	37907	31367	0	0
T11	62636	38337	0	0
T12	30780	0	0	0
T13	18089	12377	0	0
T14	14793	0	0	0
T17	0	355440	0	0
T18	0	57088	0	0
T77	0	2428	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T47,T148,T118

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T142,T149,T146

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T145,T147
1	Covered	T78,T145,T147

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T3,T12,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T77

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T77

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T12,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T12,T13,T14
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T108,T116,T94
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T150,T208
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T10,T11,T17
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T146,T200,T197
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T10,T11,T17
CheckFailError	317	Covered	T78,T145,T147
FsmStateError	289	Covered	T3,T12,T13
MacroEccCorrError	221	Covered	T47,T142,T149
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T113,T7,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T10,T11,T17
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T145,T147
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T12,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T47,T142,T149
MacroEccCorrError->NoError	235	Covered	T198,T39,T50
NoError->AccessError	256	Covered	T10,T11,T17
NoError->CheckFailError	317	Covered	T78,T145,T147
NoError->FsmStateError	289	Covered	T3,T12,T13
NoError->MacroEccCorrError	221	Covered	T47,T142,T149

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T77
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T47,T148,T118
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T208,T209,T210
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T17,T16,T105
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T11,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T142,T149,T146
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T200,T197
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T12,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T13,T77
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T13,T77
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T145,T147
1	0	Covered	T78,T145,T147
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T12,T13
1	0	Covered	T3,T12,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449476454	448616310	0	0
DigestKnown_A	449476454	448616310	0	0
DigestOffsetMustBeRepresentable_A	1144	1144	0	0
EccErrorState_A	449476454	12017	0	0
ErrorKnown_A	449476454	448616310	0	0
FsmStateKnown_A	449476454	448616310	0	0
InitDoneKnown_A	449476454	448616310	0	0
InitReadLocksPartition_A	449476454	100919699	0	0
InitWriteLocksPartition_A	449476454	100919699	0	0
OffsetMustBeBlockAligned_A	1144	1144	0	0
OtpAddrKnown_A	449476454	448616310	0	0
OtpCmdKnown_A	449476454	448616310	0	0
OtpErrorState_A	449476454	37	0	0
OtpReqKnown_A	449476454	448616310	0	0
OtpSizeKnown_A	449476454	448616310	0	0
OtpWdataKnown_A	449476454	448616310	0	0
ReadLockPropagation_A	449476454	196336457	0	0
SizeMustBeBlockAligned_A	1144	1144	0	0
TlulGntKnown_A	449476454	448616310	0	0
TlulRdataKnown_A	449476454	448616310	0	0
TlulReadOnReadLock_A	449476454	7714	0	0
TlulRerrorKnown_A	449476454	448616310	0	0
TlulRvalidKnown_A	449476454	448616310	0	0
WriteLockPropagation_A	449476454	667469	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449476454	7891380	0	0
u_state_regs_A	449476454	448616310	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	12017	0	0
T21	600091	0	0	0
T50	157050	0	0	0
T78	9400	2185	0	0
T143	0	3412	0	0
T145	0	3588	0	0
T147	0	2832	0	0
T154	166002	0	0	0
T155	9364	0	0	0
T156	18176	0	0	0
T157	9172	0	0	0
T158	10974	0	0	0
T159	54113	0	0	0
T160	12072	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	100919699	0	0
T1	88960	10740	0	0
T2	4794	140	0	0
T3	9129	3925	0	0
T4	33829	2362	0	0
T6	34875	6801	0	0
T10	37907	1037	0	0
T11	62636	1096	0	0
T12	30780	15531	0	0
T13	18089	6015	0	0
T14	14793	3945	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	100919699	0	0
T1	88960	10740	0	0
T2	4794	140	0	0
T3	9129	3925	0	0
T4	33829	2362	0	0
T6	34875	6801	0	0
T10	37907	1037	0	0
T11	62636	1096	0	0
T12	30780	15531	0	0
T13	18089	6015	0	0
T14	14793	3945	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	37	0	0
T19	370584	0	0	0
T38	315005	0	0	0
T53	12100	0	0	0
T72	467990	0	0	0
T87	16192	0	0	0
T146	0	1	0	0
T172	10548	0	0	0
T187	83275	0	0	0
T188	97042	0	0	0
T197	0	1	0	0
T200	0	1	0	0
T208	9491	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	481546	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	196336457	0	0
T1	88960	763	0	0
T2	4794	0	0	0
T3	9129	0	0	0
T4	33829	1094	0	0
T6	34875	2657	0	0
T10	37907	3366	0	0
T11	62636	22979	0	0
T12	30780	0	0	0
T13	18089	1132	0	0
T14	14793	0	0	0
T17	0	82816	0	0
T18	0	6340	0	0
T77	0	1636	0	0
T108	0	1254	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	7714	0	0
T10	37907	6	0	0
T11	62636	8	0	0
T12	30780	1	0	0
T13	18089	5	0	0
T14	14793	0	0	0
T17	666522	23	0	0
T18	73633	5	0	0
T69	48552	9	0	0
T77	10718	2	0	0
T100	0	2	0	0
T107	21695	0	0	0
T108	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	667469	0	0
T4	33829	1544	0	0
T6	34875	0	0	0
T10	37907	0	0	0
T11	62636	0	0	0
T12	30780	0	0	0
T13	18089	0	0	0
T14	14793	0	0	0
T16	0	6838	0	0
T17	666522	0	0	0
T77	10718	0	0	0
T107	21695	0	0	0
T121	0	17865	0	0
T187	0	9347	0	0
T189	0	12435	0	0
T216	0	15817	0	0
T217	0	6075	0	0
T218	0	1178	0	0
T219	0	5298	0	0
T220	0	6901	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	7891380	0	0
T4	33829	24497	0	0
T6	34875	0	0	0
T10	37907	0	0	0
T11	62636	0	0	0
T12	30780	0	0	0
T13	18089	0	0	0
T14	14793	0	0	0
T16	0	83988	0	0
T17	666522	73312	0	0
T77	10718	2411	0	0
T102	0	5355	0	0
T107	21695	0	0	0
T109	0	62507	0	0
T113	0	2622	0	0
T184	0	7304	0	0
T186	0	13127	0	0
T190	0	3262	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449476454	448616310	0	0
T1	88960	87726	0	0
T2	4794	4736	0	0
T3	9129	8872	0	0
T4	33829	33144	0	0
T6	34875	34490	0	0
T10	37907	37051	0	0
T11	62636	61944	0	0
T12	30780	30524	0	0
T13	18089	17702	0	0
T14	14793	14558	0	0