Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_otp_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.68 100.00 94.74 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.83 100.00 92.31 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.22 94.16 96.15 97.16 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 95.00 89.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT6,T11,T12
110Not Covered
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.68 94.74
tb.dut.u_otp_rsp_fifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

SCOREBRANCH
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 232830500 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1797905816 34658868 0 0
gen_passthru_fifo.paramCheckPass 7908 7908 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 232830500 0 0
T1 889600 37209 0 0
T2 47940 1132 0 0
T3 91290 6175 0 0
T4 338290 30271 0 0
T6 348750 11622 0 0
T10 379070 39577 0 0
T11 626360 31324 0 0
T12 307800 25052 0 0
T13 180890 22434 0 0
T14 147930 8249 0 0
T17 0 18611 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 889600 877260 0 0
T2 47940 47360 0 0
T3 91290 88720 0 0
T4 338290 331440 0 0
T6 348750 344900 0 0
T10 379070 370510 0 0
T11 626360 619440 0 0
T12 307800 305240 0 0
T13 180890 177020 0 0
T14 147930 145580 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 889600 877260 0 0
T2 47940 47360 0 0
T3 91290 88720 0 0
T4 338290 331440 0 0
T6 348750 344900 0 0
T10 379070 370510 0 0
T11 626360 619440 0 0
T12 307800 305240 0 0
T13 180890 177020 0 0
T14 147930 145580 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 889600 877260 0 0
T2 47940 47360 0 0
T3 91290 88720 0 0
T4 338290 331440 0 0
T6 348750 344900 0 0
T10 379070 370510 0 0
T11 626360 619440 0 0
T12 307800 305240 0 0
T13 180890 177020 0 0
T14 147930 145580 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1797905816 34658868 0 0
T1 355840 17133 0 0
T2 19176 936 0 0
T3 36516 2255 0 0
T4 135316 10015 0 0
T6 139500 4658 0 0
T10 151628 18937 0 0
T11 250544 11430 0 0
T12 123120 2848 0 0
T13 72356 4454 0 0
T14 59172 3849 0 0
T17 0 15527 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 7908 7908 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T6 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T12 6 6 0 0
T13 6 6 0 0
T14 6 6 0 0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449476454 17397512 0 0
DepthKnown_A 449476454 448616310 0 0
RvalidKnown_A 449476454 448616310 0 0
WreadyKnown_A 449476454 448616310 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449476454 17397512 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 17397512 0 0
T1 88960 16878 0 0
T2 4794 936 0 0
T3 9129 1982 0 0
T4 33829 9907 0 0
T6 34875 4420 0 0
T10 37907 18461 0 0
T11 62636 11014 0 0
T12 30780 2631 0 0
T13 18089 4298 0 0
T14 14793 3378 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 17397512 0 0
T1 88960 16878 0 0
T2 4794 936 0 0
T3 9129 1982 0 0
T4 33829 9907 0 0
T6 34875 4420 0 0
T10 37907 18461 0 0
T11 62636 11014 0 0
T12 30780 2631 0 0
T13 18089 4298 0 0
T14 14793 3378 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 58102250 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 58102250 0 0
T1 88960 5019 0 0
T2 4794 49 0 0
T3 9129 980 0 0
T4 33829 5064 0 0
T6 34875 1731 0 0
T10 37907 5160 0 0
T11 62636 4961 0 0
T12 30780 2635 0 0
T13 18089 4495 0 0
T14 14793 1082 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 45404180 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 45404180 0 0
T1 88960 5019 0 0
T2 4794 49 0 0
T3 9129 980 0 0
T4 33829 5064 0 0
T6 34875 1751 0 0
T10 37907 5160 0 0
T11 62636 4986 0 0
T12 30780 8467 0 0
T13 18089 4495 0 0
T14 14793 1118 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 24427676 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 24427676 0 0
T1 88960 13 0 0
T2 4794 0 0 0
T3 9129 13 0 0
T4 33829 6 0 0
T6 34875 12 0 0
T10 37907 42 0 0
T11 62636 38 0 0
T12 30780 19 0 0
T13 18089 28 0 0
T14 14793 19 0 0
T17 0 685 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 15881567 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 15881567 0 0
T1 88960 13 0 0
T2 4794 0 0 0
T3 9129 13 0 0
T4 33829 6 0 0
T6 34875 32 0 0
T10 37907 42 0 0
T11 62636 63 0 0
T12 30780 54 0 0
T13 18089 28 0 0
T14 14793 55 0 0
T17 0 2399 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 24833346 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 24833346 0 0
T1 88960 5006 0 0
T2 4794 49 0 0
T3 9129 967 0 0
T4 33829 5058 0 0
T6 34875 1719 0 0
T10 37907 5118 0 0
T11 62636 4923 0 0
T12 30780 2616 0 0
T13 18089 4467 0 0
T14 14793 1063 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452459364 29522613 0 0
DepthKnown_A 452459364 451543868 0 0
RvalidKnown_A 452459364 451543868 0 0
WreadyKnown_A 452459364 451543868 0 0
gen_passthru_fifo.paramCheckPass 1318 1318 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 29522613 0 0
T1 88960 5006 0 0
T2 4794 49 0 0
T3 9129 967 0 0
T4 33829 5058 0 0
T6 34875 1719 0 0
T10 37907 5118 0 0
T11 62636 4923 0 0
T12 30780 8413 0 0
T13 18089 4467 0 0
T14 14793 1063 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452459364 451543868 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1318 1318 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T3,T4
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449476454 16395521 0 0
DepthKnown_A 449476454 448616310 0 0
RvalidKnown_A 449476454 448616310 0 0
WreadyKnown_A 449476454 448616310 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449476454 16395521 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 16395521 0 0
T1 88960 121 0 0
T2 4794 0 0 0
T3 9129 130 0 0
T4 33829 51 0 0
T6 34875 113 0 0
T10 37907 217 0 0
T11 62636 189 0 0
T12 30780 99 0 0
T13 18089 64 0 0
T14 14793 226 0 0
T17 0 7421 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 16395521 0 0
T1 88960 121 0 0
T2 4794 0 0 0
T3 9129 130 0 0
T4 33829 51 0 0
T6 34875 113 0 0
T10 37907 217 0 0
T11 62636 189 0 0
T12 30780 99 0 0
T13 18089 64 0 0
T14 14793 226 0 0
T17 0 7421 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T3,T4
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449476454 636756 0 0
DepthKnown_A 449476454 448616310 0 0
RvalidKnown_A 449476454 448616310 0 0
WreadyKnown_A 449476454 448616310 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449476454 636756 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 636756 0 0
T1 88960 121 0 0
T2 4794 0 0 0
T3 9129 130 0 0
T4 33829 51 0 0
T6 34875 93 0 0
T10 37907 217 0 0
T11 62636 164 0 0
T12 30780 64 0 0
T13 18089 64 0 0
T14 14793 190 0 0
T17 0 5707 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 636756 0 0
T1 88960 121 0 0
T2 4794 0 0 0
T3 9129 130 0 0
T4 33829 51 0 0
T6 34875 93 0 0
T10 37907 217 0 0
T11 62636 164 0 0
T12 30780 64 0 0
T13 18089 64 0 0
T14 14793 190 0 0
T17 0 5707 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT6,T11,T12
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449476454 229079 0 0
DepthKnown_A 449476454 448616310 0 0
RvalidKnown_A 449476454 448616310 0 0
WreadyKnown_A 449476454 448616310 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449476454 229079 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 229079 0 0
T1 88960 13 0 0
T2 4794 0 0 0
T3 9129 13 0 0
T4 33829 6 0 0
T6 34875 32 0 0
T10 37907 42 0 0
T11 62636 63 0 0
T12 30780 54 0 0
T13 18089 28 0 0
T14 14793 55 0 0
T17 0 2399 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 448616310 0 0
T1 88960 87726 0 0
T2 4794 4736 0 0
T3 9129 8872 0 0
T4 33829 33144 0 0
T6 34875 34490 0 0
T10 37907 37051 0 0
T11 62636 61944 0 0
T12 30780 30524 0 0
T13 18089 17702 0 0
T14 14793 14558 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449476454 229079 0 0
T1 88960 13 0 0
T2 4794 0 0 0
T3 9129 13 0 0
T4 33829 6 0 0
T6 34875 32 0 0
T10 37907 42 0 0
T11 62636 63 0 0
T12 30780 54 0 0
T13 18089 28 0 0
T14 14793 55 0 0
T17 0 2399 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%