SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
85.71 | 80.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] | 57.14 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
57.14 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 3 | 4 | 57.14 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 3 | 4 | 57.14 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 3 | 4 | 57.14 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 123217 | 1 | T7 | 428 | T10 | 468 | T11 | 130 | ||||
check_fail | 2 | 1 | T161 | 1 | T173 | 1 | - | - | ||||
access_err | 51649 | 1 | T2 | 55 | T7 | 1006 | T11 | 20 | ||||
no_err | 102145 | 1 | T2 | 341 | T5 | 33 | T6 | 149 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 122654 | 1 | T7 | 428 | T10 | 468 | T11 | 130 | ||||
check_fail | 3 | 1 | T81 | 1 | T161 | 1 | T172 | 1 | ||||
access_err | 51524 | 1 | T2 | 127 | T7 | 1097 | T11 | 5 | ||||
ecc_uncorr_err | 676 | 1 | T1 | 1 | T73 | 1 | T74 | 1 | ||||
ecc_corr_err | 806 | 1 | T176 | 2 | T177 | 2 | T171 | 7 | ||||
no_err | 101362 | 1 | T2 | 269 | T5 | 33 | T6 | 149 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 122772 | 1 | T1 | 1 | T7 | 428 | T10 | 468 | ||||
check_fail | 4 | 1 | T81 | 1 | T160 | 1 | T161 | 1 | ||||
access_err | 51020 | 1 | T2 | 44 | T7 | 917 | T15 | 190 | ||||
ecc_uncorr_err | 549 | 1 | T196 | 1 | T174 | 1 | T175 | 1 | ||||
ecc_corr_err | 852 | 1 | T105 | 2 | T71 | 6 | T171 | 2 | ||||
no_err | 101712 | 1 | T2 | 352 | T5 | 33 | T6 | 149 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 122863 | 1 | T1 | 1 | T7 | 428 | T10 | 468 | ||||
check_fail | 3 | 1 | T161 | 1 | T172 | 1 | T173 | 1 | ||||
access_err | 51959 | 1 | T2 | 63 | T7 | 1028 | T11 | 26 | ||||
ecc_uncorr_err | 481 | 1 | T115 | 1 | T180 | 1 | T202 | 1 | ||||
ecc_corr_err | 1102 | 1 | T30 | 49 | T71 | 12 | T171 | 8 | ||||
no_err | 100419 | 1 | T2 | 333 | T5 | 33 | T6 | 149 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 122991 | 1 | T1 | 1 | T7 | 428 | T10 | 468 | ||||
check_fail | 3 | 1 | T81 | 1 | T160 | 1 | T172 | 1 | ||||
access_err | 51085 | 1 | T2 | 91 | T7 | 1020 | T15 | 148 | ||||
ecc_uncorr_err | 341 | 1 | T222 | 64 | T223 | 1 | T224 | 1 | ||||
ecc_corr_err | 889 | 1 | T114 | 2 | T178 | 2 | T179 | 7 | ||||
no_err | 101387 | 1 | T2 | 305 | T5 | 33 | T6 | 149 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |