Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 80.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] 57.14 1 100 1 64 64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] 85.71 1 100 1 64 64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] 85.71 1 100 1 64 64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] 85.71 1 100 1 64 64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] 85.71 1 100 1 64 64




Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
57.14 1 100 1 64 64




Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 3 4 57.14


Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 3 4 57.14 100 1 1 0



Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64




Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0



Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64




Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0



Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64




Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0



Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64




Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 3 4 57.14


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
ecc_uncorr_err 0 1 1
ecc_corr_err 0 1 1
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 123217 1 T7 428 T10 468 T11 130
check_fail 2 1 T161 1 T173 1 - -
access_err 51649 1 T2 55 T7 1006 T11 20
no_err 102145 1 T2 341 T5 33 T6 149


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 122654 1 T7 428 T10 468 T11 130
check_fail 3 1 T81 1 T161 1 T172 1
access_err 51524 1 T2 127 T7 1097 T11 5
ecc_uncorr_err 676 1 T1 1 T73 1 T74 1
ecc_corr_err 806 1 T176 2 T177 2 T171 7
no_err 101362 1 T2 269 T5 33 T6 149


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 122772 1 T1 1 T7 428 T10 468
check_fail 4 1 T81 1 T160 1 T161 1
access_err 51020 1 T2 44 T7 917 T15 190
ecc_uncorr_err 549 1 T196 1 T174 1 T175 1
ecc_corr_err 852 1 T105 2 T71 6 T171 2
no_err 101712 1 T2 352 T5 33 T6 149


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 122863 1 T1 1 T7 428 T10 468
check_fail 3 1 T161 1 T172 1 T173 1
access_err 51959 1 T2 63 T7 1028 T11 26
ecc_uncorr_err 481 1 T115 1 T180 1 T202 1
ecc_corr_err 1102 1 T30 49 T71 12 T171 8
no_err 100419 1 T2 333 T5 33 T6 149


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 122991 1 T1 1 T7 428 T10 468
check_fail 3 1 T81 1 T160 1 T172 1
access_err 51085 1 T2 91 T7 1020 T15 148
ecc_uncorr_err 341 1 T222 64 T223 1 T224 1
ecc_corr_err 889 1 T114 2 T178 2 T179 7
no_err 101387 1 T2 305 T5 33 T6 149

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%