Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25401509

1

T1

322

T2

5556

T3

20

full_word

8335707

1

T1

154

T2

3285

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33736926	1			T1	476		T2	8841		T3	26
auto[TlIntgErrCmd]	92	1			T271	4		T272	7		T273	3
auto[TlIntgErrData]	100	1			T271	2		T272	5		T273	5
auto[TlIntgErrBoth]	98	1			T271	4		T272	8		T273	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9714279

1

T1

282

T2

8011

T3

1

auto[1]

24022937

1

T1

194

T2

830

T3

25

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6108684	1			T1	202		T2	5029		T4	1079
auto[TlIntgErrNone]	partial	auto[1]	19292571	1			T1	120		T2	527		T3	20
auto[TlIntgErrNone]	full_word	auto[0]	3605465	1			T1	80		T2	2982		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	4730206	1			T1	74		T2	303		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T271	2		T272	3		T273	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T271	2		T272	2		T273	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T272	1		T373	1		T279	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T272	1		T278	1		T377	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T271	1		T272	1		T273	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T272	3		T273	1		T375	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T373	1		T378	1		T374	2
auto[TlIntgErrData]	full_word	auto[1]	10	1			T271	1		T272	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T271	3		T272	3		T375	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T271	1		T272	4		T273	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T376	1		T379	1		T377	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T272	1		T376	1		T379	1