Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	460435408	8122892	0	0
check_regwen_rd_A	460435408	1933	0	0
check_timeout_rd_A	460435408	1558	0	0
check_trigger_regwen_rd_A	460435408	2007	0	0
consistency_check_period_rd_A	460435408	2222	0	0
creator_sw_cfg_read_lock_rd_A	460435408	1567	0	0
direct_access_address_rd_A	460435408	1493	0	0
direct_access_wdata_0_rd_A	460435408	811	0	0
direct_access_wdata_1_rd_A	460435408	1070	0	0
integrity_check_period_rd_A	460435408	2072	0	0
intr_enable_rd_A	460435408	2832	0	0
owner_sw_cfg_read_lock_rd_A	460435408	1478	0	0
rot_creator_auth_codesign_read_lock_rd_A	460435408	1518	0	0
rot_creator_auth_state_read_lock_rd_A	460435408	1361	0	0
vendor_test_read_lock_rd_A	460435408	1461	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	8122892	0	0
T7	167250	317997	0	0
T9	0	98580	0	0
T10	23905	0	0	0
T11	22899	0	0	0
T12	9794	0	0	0
T13	0	86831	0	0
T15	412336	0	0	0
T17	0	44634	0	0
T29	62442	0	0	0
T37	0	77189	0	0
T73	11690	0	0	0
T79	68195	0	0	0
T112	44305	0	0	0
T113	39566	0	0	0
T232	0	20884	0	0
T280	0	127437	0	0
T281	0	71706	0	0
T282	0	42351	0	0
T283	0	49089	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1933	0	0
T9	531820	79	0	0
T13	0	56	0	0
T14	164462	0	0	0
T18	0	66	0	0
T22	0	124	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	77	0	0
T303	0	49	0	0
T304	0	66	0	0
T349	0	29	0	0
T350	0	118	0	0
T351	0	9	0	0
T352	3891	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1558	0	0
T9	531820	131	0	0
T13	0	81	0	0
T14	164462	0	0	0
T18	0	115	0	0
T22	0	136	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	121	0	0
T303	0	36	0	0
T304	0	51	0	0
T349	0	20	0	0
T350	0	73	0	0
T351	0	45	0	0
T352	3891	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	2007	0	0
T9	531820	67	0	0
T13	0	91	0	0
T14	164462	0	0	0
T18	0	51	0	0
T22	0	155	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	101	0	0
T303	0	52	0	0
T304	0	51	0	0
T349	0	32	0	0
T350	0	54	0	0
T351	0	31	0	0
T352	3891	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	2222	0	0
T9	531820	144	0	0
T13	0	97	0	0
T14	164462	0	0	0
T18	0	70	0	0
T22	0	189	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	91	0	0
T303	0	34	0	0
T304	0	46	0	0
T349	0	20	0	0
T350	0	112	0	0
T351	0	39	0	0
T352	3891	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1567	0	0
T9	531820	108	0	0
T13	0	44	0	0
T14	164462	0	0	0
T18	0	109	0	0
T22	0	95	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	125	0	0
T303	0	58	0	0
T304	0	53	0	0
T349	0	34	0	0
T350	0	96	0	0
T351	0	30	0	0
T352	3891	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1493	0	0
T9	531820	131	0	0
T13	0	82	0	0
T14	164462	0	0	0
T18	0	97	0	0
T22	0	199	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	89	0	0
T303	0	56	0	0
T304	0	57	0	0
T349	0	15	0	0
T350	0	84	0	0
T351	0	35	0	0
T352	3891	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	811	0	0
T9	531820	56	0	0
T13	0	31	0	0
T14	164462	0	0	0
T18	0	103	0	0
T22	0	119	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	64	0	0
T303	0	18	0	0
T304	0	14	0	0
T349	0	20	0	0
T350	0	55	0	0
T351	0	10	0	0
T352	3891	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1070	0	0
T9	531820	84	0	0
T13	0	48	0	0
T14	164462	0	0	0
T18	0	124	0	0
T22	0	128	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	79	0	0
T303	0	23	0	0
T304	0	27	0	0
T349	0	53	0	0
T350	0	89	0	0
T351	0	8	0	0
T352	3891	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	2072	0	0
T9	531820	137	0	0
T13	0	60	0	0
T14	164462	0	0	0
T18	0	81	0	0
T22	0	83	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	77	0	0
T303	0	31	0	0
T304	0	34	0	0
T349	0	21	0	0
T350	0	100	0	0
T351	0	61	0	0
T352	3891	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	2832	0	0
T9	531820	93	0	0
T13	0	26	0	0
T14	164462	0	0	0
T18	0	119	0	0
T22	0	183	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T121	0	42	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T241	0	35	0	0
T281	0	118	0	0
T303	0	93	0	0
T349	0	65	0	0
T352	3891	0	0	0
T353	0	32	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1478	0	0
T9	531820	137	0	0
T13	0	62	0	0
T14	164462	0	0	0
T18	0	80	0	0
T22	0	138	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	100	0	0
T303	0	33	0	0
T304	0	68	0	0
T349	0	50	0	0
T350	0	104	0	0
T351	0	24	0	0
T352	3891	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1518	0	0
T9	531820	146	0	0
T13	0	66	0	0
T14	164462	0	0	0
T18	0	77	0	0
T22	0	170	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	61	0	0
T303	0	82	0	0
T304	0	39	0	0
T349	0	17	0	0
T350	0	90	0	0
T351	0	38	0	0
T352	3891	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1361	0	0
T9	531820	92	0	0
T13	0	59	0	0
T14	164462	0	0	0
T18	0	75	0	0
T22	0	83	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	64	0	0
T303	0	39	0	0
T304	0	34	0	0
T349	0	51	0	0
T350	0	71	0	0
T351	0	16	0	0
T352	3891	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460435408	1461	0	0
T9	531820	128	0	0
T13	0	66	0	0
T14	164462	0	0	0
T18	0	95	0	0
T22	0	149	0	0
T69	7812	0	0	0
T103	64634	0	0	0
T104	95536	0	0	0
T105	102796	0	0	0
T140	11038	0	0	0
T180	14059	0	0	0
T238	39565	0	0	0
T281	0	102	0	0
T303	0	41	0	0
T304	0	81	0	0
T349	0	61	0	0
T350	0	87	0	0
T351	0	27	0	0
T352	3891	0	0	0