Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 96.55 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 96.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL292896.55
CONT_ASSIGN42100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 22 22
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 1150 1150 0 0
gen_wmask[0].MaskCheck_A 457596318 687784 0 0
gen_wmask[10].MaskCheck_A 457596318 687784 0 0
gen_wmask[11].MaskCheck_A 457596318 687784 0 0
gen_wmask[12].MaskCheck_A 457596318 687784 0 0
gen_wmask[13].MaskCheck_A 457596318 687784 0 0
gen_wmask[14].MaskCheck_A 457596318 687784 0 0
gen_wmask[15].MaskCheck_A 457596318 687784 0 0
gen_wmask[16].MaskCheck_A 457596318 687784 0 0
gen_wmask[17].MaskCheck_A 457596318 687784 0 0
gen_wmask[18].MaskCheck_A 457596318 687784 0 0
gen_wmask[19].MaskCheck_A 457596318 687784 0 0
gen_wmask[1].MaskCheck_A 457596318 687784 0 0
gen_wmask[20].MaskCheck_A 457596318 687784 0 0
gen_wmask[21].MaskCheck_A 457596318 687784 0 0
gen_wmask[2].MaskCheck_A 457596318 687784 0 0
gen_wmask[3].MaskCheck_A 457596318 687784 0 0
gen_wmask[4].MaskCheck_A 457596318 687784 0 0
gen_wmask[5].MaskCheck_A 457596318 687784 0 0
gen_wmask[6].MaskCheck_A 457596318 687784 0 0
gen_wmask[7].MaskCheck_A 457596318 687784 0 0
gen_wmask[8].MaskCheck_A 457596318 687784 0 0
gen_wmask[9].MaskCheck_A 457596318 687784 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[10].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[11].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[12].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[13].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[14].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[15].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[16].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[17].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[18].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[19].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[20].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[21].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[4].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[5].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[6].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[7].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[8].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

gen_wmask[9].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 687784 0 0
T1 13524 60 0 0
T2 93839 236 0 0
T3 4148 0 0 0
T4 13094 90 0 0
T5 24791 136 0 0
T6 28080 228 0 0
T7 167250 7910 0 0
T10 23905 0 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 1272 0 0
T29 0 250 0 0
T79 0 56 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%