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Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.65 98.00 93.75 91.67 95.38 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.99 98.54 93.75 100.00 91.67 96.25 95.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.19 94.16 96.15 97.02 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_digest_read_lock.u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
u_otp_ctrl_ecc_reg 100.00 100.00 100.00 100.00 100.00
u_prim_count 100.00 100.00
u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.gen_partitions[7].gen_buffered.u_part_buf
Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf
Line No.TotalCoveredPercent
TOTAL15014798.00
CONT_ASSIGN18211100.00
CONT_ASSIGN19311100.00
ALWAYS20613012797.69
CONT_ASSIGN63611100.00
CONT_ASSIGN64111100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN64611100.00
CONT_ASSIGN65211100.00
CONT_ASSIGN67511100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN68011100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN72911100.00
ALWAYS75033100.00
ALWAYS75355100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
182 1 1
193 1 1
206 1 1
209 1 1
212 1 1
215 1 1
218 1 1
219 1 1
220 1 1
221 1 1
224 1 1
225 1 1
226 1 1
229 1 1
230 1 1
233 1 1
234 1 1
237 1 1
238 1 1
240 1 1
245 1 1
246 1 1
MISSING_ELSE
254 1 1
255 1 1
256 1 1
MISSING_ELSE
265 1 1
266 1 1
267 1 1
271 1 1
272 1 1
275 1 1
276 1 1
278 unreachable
279 unreachable
282 1 1
283 1 1
MISSING_ELSE
286 1 1
287 1 1
MISSING_ELSE
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
MISSING_ELSE
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
MISSING_ELSE
324 1 1
325 1 1
326 1 1
331 unreachable
333 1 1
334 1 1
335 1 1
MISSING_ELSE
343 1 1
348 1 1
349 1 1
==> MISSING_ELSE
351 1 1
352 1 1
MISSING_ELSE
362 1 1
363 1 1
366 1 1
368 1 1
369 1 1
370 1 1
373 0 1
374 0 1
376 0 1
381 unreachable
385 unreachable
386 unreachable
387 unreachable
390 unreachable
391 unreachable
394 unreachable
395 unreachable
397 unreachable
401 1 1
402 1 1
MISSING_ELSE
405 1 1
406 1 1
408 1 1
MISSING_ELSE
417 1 1
418 1 1
419 1 1
420 1 1
423 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
432 unreachable
433 unreachable
434 unreachable
==> MISSING_ELSE
443 unreachable
444 unreachable
445 unreachable
==> MISSING_ELSE
455 1 1
456 1 1
457 1 1
458 1 1
459 1 1
460 1 1
MISSING_ELSE
467 1 1
468 1 1
469 1 1
470 1 1
MISSING_ELSE
480 1 1
481 1 1
482 1 1
483 1 1
485 1 1
489 1 1
490 1 1
491 1 1
493 excluded
Exclude Annotation: VC_COV_UNR
494 excluded
Exclude Annotation: VC_COV_UNR
498 1 1
499 1 1
MISSING_ELSE
503 1 1
504 1 1
==> MISSING_ELSE
==> MISSING_ELSE
516 excluded
Exclude Annotation: VC_COV_UNR
517 excluded
Exclude Annotation: VC_COV_UNR
518 excluded
Exclude Annotation: VC_COV_UNR
519 excluded
Exclude Annotation: VC_COV_UNR
520 excluded
Exclude Annotation: VC_COV_UNR
==> MISSING_ELSE
528 1 1
529 1 1
530 1 1
531 1 1
532 1 1
MISSING_ELSE
542 1 1
543 1 1
544 1 1
547 1 1
548 1 1
551 1 1
552 1 1
556 1 1
560 1 1
561 1 1
563 1 1
MISSING_ELSE
572 1 1
573 1 1
574 1 1
MISSING_ELSE
578 1 1
579 1 1
595 1 1
596 excluded
Exclude Annotation: VC_COV_UNR
597 excluded
Exclude Annotation: VC_COV_UNR
598 excluded
Exclude Annotation: VC_COV_UNR
==> MISSING_ELSE
MISSING_ELSE
602 1 1
603 1 1
604 1 1
605 1 1
606 1 1
MISSING_ELSE
MISSING_ELSE
636 1 1
641 1 1
642 1 1
646 1 1
652 1 1
675 1 1
678 1 1
680 1 1
709 1 1
729 1 1
750 3 3
753 1 1
754 1 1
756 1 1
758 1 1
759 1 1


Cond Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf
TotalCoveredPercent
Conditions484593.75
Logical484593.75
Non-Logical00
Event00

 LINE       271
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       282
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT51,T28,T52

 LINE       302
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T3

 LINE       368
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------
-1--2-StatusTests
00Not Covered
01CoveredT7,T9,T13
10CoveredT2,T15,T29

 LINE       368
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------
-1-StatusTests
0CoveredT7,T9,T13
1CoveredT2,T5,T6

 LINE       368
 SUB-EXPRESSION (digest_o == '0)
                --------1-------
-1-StatusTests
0CoveredT2,T15,T29
1CoveredT2,T5,T6

 LINE       385
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------
-1-StatusTests
0Unreachable
1Unreachable

 LINE       401
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT53,T54

 LINE       426
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T3

 LINE       433
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       485
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       547
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------
-1--2-StatusTests
00CoveredT55,T56,T57
01CoveredT1,T2,T3
10CoveredT2,T4,T6

 LINE       547
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       547
 SUB-EXPRESSION (digest_o == '0)
                --------1-------
-1-StatusTests
0CoveredT2,T4,T6
1CoveredT1,T2,T3

 LINE       573
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T4,T7
1CoveredT23,T24,T25

 LINE       597
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1Excluded VC_COV_UNR

 LINE       605
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT1,T4,T7
1CoveredT1,T4,T7

 LINE       636
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011010000)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T6

 LINE       636
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T6

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       678
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       709
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       709
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       729
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       729
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

FSM Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf
Summary for FSM :: state_q
TotalCoveredPercent
States 15 15 100.00 (Not included in score)
Transitions 31 29 93.55
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTestsExclude Annotation
CnstyReadSt 334 Covered T2,T5,T6
CnstyReadWaitSt 352 Covered T2,T5,T6
ErrorSt 286 Covered T1,T4,T7
IdleSt 369 Covered T1,T2,T3
InitDescrSt 276 Covered T1,T2,T3
InitDescrWaitSt 303 Covered T1,T2,T3
InitSt 246 Covered T1,T2,T3
InitWaitSt 256 Covered T1,T2,T3
IntegDigClrSt 272 Covered T1,T2,T3
IntegDigFinSt 491 Covered T1,T2,T3
IntegDigPadSt 493 Excluded VC_COV_UNR
IntegDigSt 434 Covered T1,T2,T3
IntegDigWaitSt 532 Covered T1,T2,T3
IntegScrSt 427 Covered T1,T2,T3
IntegScrWaitSt 460 Covered T1,T2,T3
ResetSt 244 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
CnstyReadSt->CnstyReadWaitSt 352 Covered T2,T5,T6
CnstyReadSt->ErrorSt 596 Covered T69,T70,T31
CnstyReadWaitSt->CnstyReadSt 390 Excluded VC_COV_UNR
CnstyReadWaitSt->ErrorSt 373 Covered T31,T83,T125
CnstyReadWaitSt->IdleSt 369 Covered T2,T5,T6
IdleSt->CnstyReadSt 334 Covered T2,T5,T6
IdleSt->ErrorSt 596 Covered T4,T7,T10
IdleSt->IntegDigClrSt 326 Covered T2,T5,T6
InitDescrSt->ErrorSt 596 Covered T42,T124,T51
InitDescrSt->InitDescrWaitSt 303 Covered T1,T2,T3
InitDescrWaitSt->ErrorSt 596 Covered T48,T49,T50
InitDescrWaitSt->InitSt 315 Covered T1,T2,T3
InitSt->ErrorSt 596 Covered T1,T73,T74
InitSt->InitWaitSt 256 Covered T1,T2,T3
InitWaitSt->ErrorSt 286 Covered T76,T84,T85
InitWaitSt->InitDescrSt 276 Covered T1,T2,T3
InitWaitSt->InitSt 278 Excluded VC_COV_UNR
InitWaitSt->IntegDigClrSt 272 Covered T1,T2,T3
IntegDigClrSt->ErrorSt 596 Covered T7,T15,T13
IntegDigClrSt->IdleSt 443 Excluded VC_COV_UNR
IntegDigClrSt->IntegDigSt 434 Excluded VC_COV_UNR
IntegDigClrSt->IntegScrSt 427 Covered T1,T2,T3
IntegDigFinSt->ErrorSt 596 Not Covered
IntegDigFinSt->IntegDigWaitSt 532 Covered T1,T2,T3
IntegDigPadSt->ErrorSt 596 Excluded
IntegDigPadSt->IntegDigFinSt 520 Excluded
IntegDigSt->ErrorSt 596 Covered T126,T127
IntegDigSt->IntegDigFinSt 491 Covered T1,T2,T3
IntegDigSt->IntegDigPadSt 493 Excluded
IntegDigSt->IntegScrSt 504 Covered T1,T2,T3
IntegDigWaitSt->ErrorSt 560 Covered T55,T56,T57
IntegDigWaitSt->IdleSt 548 Covered T1,T2,T3
IntegScrSt->ErrorSt 596 Not Covered
IntegScrSt->IntegScrWaitSt 460 Covered T1,T2,T3
IntegScrWaitSt->ErrorSt 596 Covered T7,T92,T93
IntegScrWaitSt->IntegDigSt 470 Covered T1,T2,T3
ResetSt->ErrorSt 596 Covered T80,T81,T82
ResetSt->InitSt 246 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 5 4 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
CheckFailError 374 Covered T55,T56,T57
FsmStateError 574 Covered T1,T4,T7
MacroEccCorrError 283 Covered T51,T28,T52
NoError 573 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
CheckFailError->FsmStateError 606 Excluded VC_COV_UNR
CheckFailError->MacroEccCorrError 283 Excluded VC_COV_UNR
FsmStateError->CheckFailError 374 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 283 Excluded VC_COV_UNR
MacroEccCorrError->CheckFailError 374 Not Covered
MacroEccCorrError->FsmStateError 606 Covered T51,T28,T52
NoError->CheckFailError 374 Covered T55,T56,T57
NoError->FsmStateError 574 Covered T1,T4,T7
NoError->MacroEccCorrError 283 Covered T51,T28,T52



Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf
Line No.TotalCoveredPercent
Branches 65 62 95.38
TERNARY 636 2 2 100.00
TERNARY 652 2 2 100.00
TERNARY 678 2 2 100.00
TERNARY 709 2 2 100.00
TERNARY 729 2 2 100.00
CASE 240 47 44 93.62
IF 595 1 1 100.00
IF 602 3 3 100.00
IF 750 2 2 100.00
IF 753 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 636 ((base_sel == DigOffset)) ?

Branches:
-1-StatusTests
1 Covered T2,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 652 ((data_sel == ScrmblData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 678 (init_done_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 709 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 729 ((digest_o != '0)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 240 case (state_q) -2-: 245 if (init_req_i) -3-: 255 if (otp_gnt_i) -4-: 265 if (otp_rvalid_i) -5-: 267 if ((otp_err inside {NoError, MacroEccCorrError})) -6-: 271 if ((cnt == LastScrmblBlock)) -7-: 275 if (1'b1) -8-: 282 if ((otp_err != NoError)) -9-: 302 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -10-: 314 if (scrmbl_valid_i) -11-: 324 if (integ_chk_req_i) -12-: 325 if (1'b1) -13-: 333 if (cnsty_chk_req_i) -14-: 348 if (1'b1) -15-: 351 if (otp_gnt_i) -16-: 362 if (otp_rvalid_i) -17-: 363 if ((otp_err inside {NoError, MacroEccCorrError})) -18-: 366 if (1'b1) -19-: 368 if (((digest_o == data_mux) || (digest_o == '0))) -20-: 381 if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i))) -21-: 385 if ((cnt == LastScrmblBlock)) -22-: 401 if ((otp_err != NoError)) -23-: 417 if (1'b1) -24-: 424 if (1'b1) -25-: 426 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -26-: 433 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -27-: 444 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q)) -28-: 459 if (scrmbl_ready_i) -29-: 469 if (scrmbl_valid_i) -30-: 482 if (scrmbl_ready_i) -31-: 485 if ((cnt == PenultimateScrmblBlock)) -32-: 489 if (cnt[0]) -33-: 498 if (cnt[0]) -34-: 503 if (1'b1) -35-: 519 if (scrmbl_ready_i) -36-: 531 if (scrmbl_ready_i) -37-: 544 if (scrmbl_valid_i) -38-: 547 if (((digest_o == data_mux) || (digest_o == '0))) -39-: 551 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q)) -40-: 573 if ((error_q == NoError))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40-StatusTestsExclude Annotation
ResetSt 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
InitWaitSt - - 1 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T51,T28,T52
InitWaitSt - - 1 1 - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T128,T129,T44
InitWaitSt - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitDescrSt - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitDescrSt - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitDescrWaitSt - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitDescrWaitSt - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
IdleSt - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unreachable
IdleSt - - - - - - - - - 0 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
IdleSt - - - - - - - - - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
CnstyReadSt - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
CnstyReadSt - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
CnstyReadSt - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
CnstyReadSt - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - - - Not Covered
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 1 1 - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 1 0 - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 0 - 0 - - - - - - - - - - - - - - - - - - - - Unreachable
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 - - - - 1 - - - - - - - - - - - - - - - - - - Covered T53,T54
CnstyReadWaitSt - - - - - - - - - - - - - - 1 1 - - - - 0 - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
CnstyReadWaitSt - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T31,T83,T125
CnstyReadWaitSt - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T5,T6
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - - - - - - - - - Unreachable
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - - - - - - - - - Excluded VC_COV_UNR
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - - - - - - - - - - Unreachable
IntegDigClrSt - - - - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - - - - - - - - - Excluded VC_COV_UNR
IntegScrSt - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T1,T2,T3
IntegScrSt - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T1,T2,T3
IntegScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Covered T1,T2,T3
IntegScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - Covered T1,T2,T3
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - - Not Covered
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - - Covered T1,T2,T3
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - - Covered T1,T2,T3
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - 1 - - - - - - Covered T1,T2,T3
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - 0 - - - - - - Excluded VC_COV_UNR
IntegDigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - Not Covered
IntegDigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Excluded VC_COV_UNR
IntegDigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - Excluded VC_COV_UNR
IntegDigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - Covered T1,T2,T3
IntegDigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - Covered T1,T2,T3
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - Covered T1,T2,T3
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - Covered T2,T5,T6
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - Covered T55,T56,T57
IntegDigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T23,T24,T25
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T1,T4,T7
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T23,T24,T25


LineNo. Expression -1-: 595 if (ecc_err) -2-: 597 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTestsExclude Annotation
1 1 Excluded VC_COV_UNR
1 0 Excluded VC_COV_UNR
0 - Covered T1,T2,T3


LineNo. Expression -1-: 602 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err)) -2-: 605 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T7
1 0 Covered T1,T4,T7
0 - Covered T1,T2,T3


LineNo. Expression -1-: 750 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 753 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 35 97.22 34 94.44
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 35 97.22 34 94.44




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccessKnown_A 457596318 456759280 0 0
BypassEnable0_A 457596318 456759280 0 0
BypassEnable1_A 457596318 456759280 0 0
CnstyChkAckKnown_A 457596318 456759280 0 0
DataKnown_A 457596318 456759280 0 0
DigestKnown_A 457596318 456759280 0 0
DigestOffsetMustBeRepresentable_A 1150 1150 0 0
EccErrorState_A 457596318 0 0 0
ErrorKnown_A 457596318 456759280 0 0
InitDoneKnown_A 457596318 456759280 0 0
InitReadLocksPartition_A 457596318 112409488 0 0
InitWriteLocksPartition_A 457596318 112409488 0 0
IntegChkAckKnown_A 457596318 456759280 0 0
OffsetMustBeBlockAligned_A 1150 1150 0 0
OtpAddrKnown_A 457596318 456759280 0 0
OtpCmdKnown_A 457596318 456759280 0 0
OtpErrorState_A 0 0 0 0
OtpPartBufSize_A 1150 1150 0 0
OtpReqKnown_A 457596318 456759280 0 0
OtpSizeKnown_A 457596318 456759280 0 0
OtpWdataKnown_A 457596318 456759280 0 0
ReadLockImpliesDigest_A 457596318 456759280 0 0
ReadLockPropagation_A 457596318 2540032 0 0
ScrambledImpliesDigest_A 457596318 456759280 0 0
ScrmblCmdKnown_A 457596318 456759280 0 0
ScrmblDataKnown_A 457596318 456759280 0 0
ScrmblModeKnown_A 457596318 456759280 0 0
ScrmblMtxReqKnown_A 457596318 456759280 0 0
ScrmblSelKnown_A 457596318 456759280 0 0
ScrmblValidKnown_A 457596318 456759280 0 0
SizeMustBeBlockAligned_A 1150 1150 0 0
WriteLockImpliesDigest_A 457596318 456759280 0 0
WriteLockPropagation_A 457596318 2583633 0 0
gen_digest_read_lock.DigestReadLocksPartition_A 457596318 27532682 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 457596318 27532682 0 0
u_state_regs_A 457596318 456759280 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

BypassEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

BypassEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

CnstyChkAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 112409488 0 0
T1 13524 5467 0 0
T2 93839 11679 0 0
T3 4148 901 0 0
T4 13094 7052 0 0
T5 24791 6247 0 0
T6 28080 3699 0 0
T7 167250 528821 0 0
T10 23905 18516 0 0
T11 22899 10679 0 0
T12 9794 1081 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 112409488 0 0
T1 13524 5467 0 0
T2 93839 11679 0 0
T3 4148 901 0 0
T4 13094 7052 0 0
T5 24791 6247 0 0
T6 28080 3699 0 0
T7 167250 528821 0 0
T10 23905 18516 0 0
T11 22899 10679 0 0
T12 9794 1081 0 0

IntegChkAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

OtpPartBufSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ReadLockImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 2540032 0 0
T2 93839 8045 0 0
T3 4148 0 0 0
T4 13094 0 0 0
T5 24791 0 0 0
T6 28080 0 0 0
T7 167250 0 0 0
T10 23905 0 0 0
T11 22899 0 0 0
T12 9794 0 0 0
T15 412336 5596 0 0
T16 0 7718 0 0
T103 0 1468 0 0
T104 0 7071 0 0
T107 0 3866 0 0
T108 0 2336 0 0
T109 0 8693 0 0
T110 0 28804 0 0
T111 0 828 0 0

ScrambledImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

WriteLockImpliesDigest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 2583633 0 0
T2 93839 8045 0 0
T3 4148 0 0 0
T4 13094 0 0 0
T5 24791 0 0 0
T6 28080 0 0 0
T7 167250 0 0 0
T10 23905 0 0 0
T11 22899 0 0 0
T12 9794 0 0 0
T15 412336 8352 0 0
T16 0 5717 0 0
T103 0 822 0 0
T104 0 15386 0 0
T106 0 3276 0 0
T109 0 7208 0 0
T110 0 58146 0 0
T111 0 3307 0 0
T117 0 1689 0 0

gen_digest_read_lock.DigestReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 27532682 0 0
T2 93839 58025 0 0
T3 4148 0 0 0
T4 13094 3682 0 0
T5 24791 0 0 0
T6 28080 3823 0 0
T7 167250 0 0 0
T10 23905 0 0 0
T11 22899 0 0 0
T12 9794 0 0 0
T15 412336 163893 0 0
T16 0 100283 0 0
T29 0 33232 0 0
T79 0 56216 0 0
T103 0 40460 0 0
T113 0 4637 0 0
T116 0 22646 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 27532682 0 0
T2 93839 58025 0 0
T3 4148 0 0 0
T4 13094 3682 0 0
T5 24791 0 0 0
T6 28080 3823 0 0
T7 167250 0 0 0
T10 23905 0 0 0
T11 22899 0 0 0
T12 9794 0 0 0
T15 412336 163893 0 0
T16 0 100283 0 0
T29 0 33232 0 0
T79 0 56216 0 0
T103 0 40460 0 0
T113 0 4637 0 0
T116 0 22646 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%