Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T161,T173
1	Covered	T161,T173

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T10
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T15

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T15

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T7
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T209,T210,T211
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T7,T11
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T80,T81,T82
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T7,T11
CheckFailError	317	Covered	T161,T173
FsmStateError	289	Covered	T1,T4,T7
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T7,T8,T149
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T7,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T161,T173
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T4,T7
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T7,T11
NoError->CheckFailError	317	Covered	T161,T173
NoError->FsmStateError	289	Covered	T1,T4,T7
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T106,T107,T108
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T7,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T161,T173
1	0	Covered	T161,T173
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457596318	456759280	0	0
DigestKnown_A	457596318	456759280	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457596318	6485	0	0
ErrorKnown_A	457596318	456759280	0	0
FsmStateKnown_A	457596318	456759280	0	0
InitDoneKnown_A	457596318	456759280	0	0
InitReadLocksPartition_A	457596318	104345933	0	0
InitWriteLocksPartition_A	457596318	104345933	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457596318	456759280	0	0
OtpCmdKnown_A	457596318	456759280	0	0
OtpErrorState_A	457596318	0	0	0
OtpReqKnown_A	457596318	456759280	0	0
OtpSizeKnown_A	457596318	456759280	0	0
OtpWdataKnown_A	457596318	456759280	0	0
ReadLockPropagation_A	457596318	203210740	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457596318	456759280	0	0
TlulRdataKnown_A	457596318	456759280	0	0
TlulReadOnReadLock_A	457596318	7943	0	0
TlulRerrorKnown_A	457596318	456759280	0	0
TlulRvalidKnown_A	457596318	456759280	0	0
WriteLockPropagation_A	457596318	2019509	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457596318	29602455	0	0
u_state_regs_A	457596318	456759280	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	6485	0	0
T161	11724	3206	0	0
T173	0	3279	0	0
T186	122007	0	0	0
T187	56011	0	0	0
T188	8820	0	0	0
T189	47677	0	0	0
T190	56401	0	0	0
T191	39796	0	0	0
T192	89770	0	0	0
T193	699879	0	0	0
T194	15001	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104345933	0	0
T1	13524	3812	0	0
T2	93839	3439	0	0
T3	4148	77	0	0
T4	13094	5405	0	0
T5	24791	1008	0	0
T6	28080	345	0	0
T7	167250	527833	0	0
T10	23905	16869	0	0
T11	22899	6560	0	0
T12	9794	257	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104345933	0	0
T1	13524	3812	0	0
T2	93839	3439	0	0
T3	4148	77	0	0
T4	13094	5405	0	0
T5	24791	1008	0	0
T6	28080	345	0	0
T7	167250	527833	0	0
T10	23905	16869	0	0
T11	22899	6560	0	0
T12	9794	257	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	203210740	0	0
T2	93839	27430	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	626557	0	0
T10	23905	0	0	0
T11	22899	2020	0	0
T12	9794	0	0	0
T15	412336	65380	0	0
T16	0	4668	0	0
T29	0	6849	0	0
T79	0	6297	0	0
T114	0	1431	0	0
T116	0	35091	0	0
T139	0	1846	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	7943	0	0
T2	93839	6	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	77	0	0
T10	23905	11	0	0
T11	22899	10	0	0
T12	9794	0	0	0
T15	412336	13	0	0
T29	0	2	0	0
T79	0	15	0	0
T114	0	3	0	0
T116	0	6	0	0
T139	0	12	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	2019509	0	0
T2	93839	18614	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	0	0	0
T10	23905	0	0	0
T11	22899	0	0	0
T12	9794	0	0	0
T15	412336	13301	0	0
T16	0	5913	0	0
T29	0	10934	0	0
T106	0	3282	0	0
T108	0	25595	0	0
T109	0	5658	0	0
T111	0	4136	0	0
T117	0	4564	0	0
T178	0	8594	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	29602455	0	0
T2	93839	75933	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	0	0	0
T10	23905	0	0	0
T11	22899	14730	0	0
T12	9794	0	0	0
T15	412336	188155	0	0
T16	0	51570	0	0
T29	0	46592	0	0
T74	0	3745	0	0
T79	0	57463	0	0
T104	0	27244	0	0
T116	0	57543	0	0
T180	0	3808	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T174,T175,T76

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T176,T177,T171

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T161,T172
1	Covered	T81,T161,T172

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T4,T7,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T10
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T7,T10
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T209,T210,T211
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T73,T74
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T7,T11
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T105,T176,T167
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T80,T81,T82
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T7,T11
CheckFailError	317	Covered	T81,T161,T172
FsmStateError	289	Covered	T4,T7,T10
MacroEccCorrError	221	Covered	T174,T175,T76
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T11,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T7,T15
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T161,T172
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T7,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T174,T175,T76
MacroEccCorrError->NoError	235	Covered	T176,T177,T212
NoError->AccessError	256	Covered	T2,T7,T11
NoError->CheckFailError	317	Covered	T81,T161,T172
NoError->FsmStateError	289	Covered	T4,T7,T10
NoError->MacroEccCorrError	221	Covered	T174,T175,T76

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T174,T175,T76
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T73,T74
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T108,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T7,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T176,T177,T171
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T105,T176,T167
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T161,T172
1	0	Covered	T81,T161,T172
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T7,T10
1	0	Covered	T1,T4,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457596318	456759280	0	0
DigestKnown_A	457596318	456759280	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457596318	9626	0	0
ErrorKnown_A	457596318	456759280	0	0
FsmStateKnown_A	457596318	456759280	0	0
InitDoneKnown_A	457596318	456759280	0	0
InitReadLocksPartition_A	457596318	104522608	0	0
InitWriteLocksPartition_A	457596318	104522608	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457596318	456759280	0	0
OtpCmdKnown_A	457596318	456759280	0	0
OtpErrorState_A	457596318	79	0	0
OtpReqKnown_A	457596318	456759280	0	0
OtpSizeKnown_A	457596318	456759280	0	0
OtpWdataKnown_A	457596318	456759280	0	0
ReadLockPropagation_A	457596318	203069663	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457596318	456759280	0	0
TlulRdataKnown_A	457596318	456759280	0	0
TlulReadOnReadLock_A	457596318	8334	0	0
TlulRerrorKnown_A	457596318	456759280	0	0
TlulRvalidKnown_A	457596318	456759280	0	0
WriteLockPropagation_A	457596318	2283245	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457596318	29836953	0	0
u_state_regs_A	457596318	456759280	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	9626	0	0
T31	63490	0	0	0
T56	12156	0	0	0
T71	31703	0	0	0
T81	9070	2451	0	0
T161	0	3206	0	0
T172	0	3969	0	0
T177	26434	0	0	0
T181	16302	0	0	0
T182	12403	0	0	0
T183	13684	0	0	0
T184	10125	0	0	0
T185	11811	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104522608	0	0
T1	13524	3853	0	0
T2	93839	3609	0	0
T3	4148	94	0	0
T4	13094	5439	0	0
T5	24791	1127	0	0
T6	28080	447	0	0
T7	167250	527853	0	0
T10	23905	16903	0	0
T11	22899	6645	0	0
T12	9794	274	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104522608	0	0
T1	13524	3853	0	0
T2	93839	3609	0	0
T3	4148	94	0	0
T4	13094	5439	0	0
T5	24791	1127	0	0
T6	28080	447	0	0
T7	167250	527853	0	0
T10	23905	16903	0	0
T11	22899	6645	0	0
T12	9794	274	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	79	0	0
T1	13524	1	0	0
T2	93839	0	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	0	0	0
T10	23905	0	0	0
T11	22899	0	0	0
T12	9794	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T105	0	2	0	0
T140	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T195	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	203069663	0	0
T2	93839	39576	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	626046	0	0
T8	0	11704	0	0
T9	0	517949	0	0
T10	23905	0	0	0
T11	22899	7448	0	0
T12	9794	0	0	0
T15	412336	50127	0	0
T16	0	5949	0	0
T29	0	2746	0	0
T79	0	4036	0	0
T116	0	26580	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	8334	0	0
T2	93839	12	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	77	0	0
T10	23905	15	0	0
T11	22899	6	0	0
T12	9794	0	0	0
T15	412336	19	0	0
T16	0	1	0	0
T79	0	20	0	0
T114	0	5	0	0
T116	0	7	0	0
T139	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	2283245	0	0
T2	93839	8045	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	0	0	0
T10	23905	0	0	0
T11	22899	6261	0	0
T12	9794	0	0	0
T15	412336	31595	0	0
T29	0	5111	0	0
T106	0	3523	0	0
T107	0	3983	0	0
T108	0	49716	0	0
T109	0	8408	0	0
T116	0	13919	0	0
T117	0	3208	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	29836953	0	0
T1	13524	2890	0	0
T2	93839	75780	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	0	0	0
T10	23905	0	0	0
T11	22899	14679	0	0
T12	9794	0	0	0
T15	0	198185	0	0
T16	0	23309	0	0
T29	0	36598	0	0
T73	0	3497	0	0
T74	0	3740	0	0
T79	0	57412	0	0
T116	0	57424	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T115,T180,T72

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T105,T71,T171

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T160,T161
1	Covered	T81,T160,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T10
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111011000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T29,T16

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T29,T16

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T7,T10
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T209,T210,T211
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T73,T74
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T7,T15
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T171,T198,T200
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T80,T81,T82
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T7,T15
CheckFailError	317	Covered	T81,T160,T161
FsmStateError	289	Covered	T1,T4,T7
MacroEccCorrError	221	Covered	T115,T180,T105
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T9,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T7,T15
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T160,T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T115,T180,T72
MacroEccCorrError->NoError	235	Covered	T105,T71,T171
NoError->AccessError	256	Covered	T2,T7,T15
NoError->CheckFailError	317	Covered	T81,T160,T161
NoError->FsmStateError	289	Covered	T1,T4,T7
NoError->MacroEccCorrError	221	Covered	T115,T180,T105

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T29,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T115,T180,T72
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T196,T174,T175
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T106,T107,T13
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T7,T15
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T105,T71,T171
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T171,T198,T200
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T10,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T160,T161
1	0	Covered	T81,T160,T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457596318	456759280	0	0
DigestKnown_A	457596318	456759280	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457596318	12891	0	0
ErrorKnown_A	457596318	456759280	0	0
FsmStateKnown_A	457596318	456759280	0	0
InitDoneKnown_A	457596318	456759280	0	0
InitReadLocksPartition_A	457596318	104698120	0	0
InitWriteLocksPartition_A	457596318	104698120	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457596318	456759280	0	0
OtpCmdKnown_A	457596318	456759280	0	0
OtpErrorState_A	457596318	54	0	0
OtpReqKnown_A	457596318	456759280	0	0
OtpSizeKnown_A	457596318	456759280	0	0
OtpWdataKnown_A	457596318	456759280	0	0
ReadLockPropagation_A	457596318	205025740	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457596318	456759280	0	0
TlulRdataKnown_A	457596318	456759280	0	0
TlulReadOnReadLock_A	457596318	8398	0	0
TlulRerrorKnown_A	457596318	456759280	0	0
TlulRvalidKnown_A	457596318	456759280	0	0
WriteLockPropagation_A	457596318	1240762	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457596318	19717926	0	0
u_state_regs_A	457596318	456759280	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	12891	0	0
T31	63490	0	0	0
T56	12156	0	0	0
T71	31703	0	0	0
T81	9070	2451	0	0
T160	0	3265	0	0
T161	0	3206	0	0
T172	0	3969	0	0
T177	26434	0	0	0
T181	16302	0	0	0
T182	12403	0	0	0
T183	13684	0	0	0
T184	10125	0	0	0
T185	11811	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104698120	0	0
T1	13524	3887	0	0
T2	93839	3779	0	0
T3	4148	111	0	0
T4	13094	5473	0	0
T5	24791	1246	0	0
T6	28080	539	0	0
T7	167250	527874	0	0
T10	23905	16937	0	0
T11	22899	6730	0	0
T12	9794	291	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	104698120	0	0
T1	13524	3887	0	0
T2	93839	3779	0	0
T3	4148	111	0	0
T4	13094	5473	0	0
T5	24791	1246	0	0
T6	28080	539	0	0
T7	167250	527874	0	0
T10	23905	16937	0	0
T11	22899	6730	0	0
T12	9794	291	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	54	0	0
T13	549254	0	0	0
T99	0	1	0	0
T107	66291	0	0	0
T108	663208	0	0	0
T117	66578	0	0	0
T167	0	1	0	0
T170	58754	0	0	0
T171	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T185	0	1	0	0
T196	10173	1	0	0
T197	17385	0	0	0
T198	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	9477	0	0	0
T203	25973	0	0	0
T204	25919	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	205025740	0	0
T2	93839	26573	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	570546	0	0
T9	0	500268	0	0
T10	23905	0	0	0
T11	22899	8118	0	0
T12	9794	0	0	0
T15	412336	53526	0	0
T16	0	2828	0	0
T29	0	14303	0	0
T79	0	6291	0	0
T116	0	23886	0	0
T139	0	1844	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	8398	0	0
T2	93839	3	0	0
T3	4148	0	0	0
T4	13094	0	0	0
T5	24791	0	0	0
T6	28080	0	0	0
T7	167250	45	0	0
T10	23905	24	0	0
T11	22899	4	0	0
T12	9794	0	0	0
T15	412336	19	0	0
T29	0	2	0	0
T79	0	24	0	0
T114	0	3	0	0
T116	0	2	0	0
T139	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	1240762	0	0
T16	134782	1523	0	0
T29	62442	11292	0	0
T73	11690	0	0	0
T74	11230	0	0	0
T107	0	6926	0	0
T108	0	28500	0	0
T109	0	8608	0	0
T110	0	28804	0	0
T111	0	3251	0	0
T112	44305	0	0	0
T113	39566	0	0	0
T114	29741	0	0	0
T115	13270	0	0	0
T116	73203	0	0	0
T134	0	1820	0	0
T139	44481	0	0	0
T206	0	10027	0	0
T207	0	4164	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	19717926	0	0
T15	412336	9147	0	0
T16	0	74386	0	0
T29	62442	46354	0	0
T30	0	28042	0	0
T73	11690	0	0	0
T74	11230	0	0	0
T79	68195	0	0	0
T107	0	55471	0	0
T108	0	122025	0	0
T112	44305	0	0	0
T113	39566	0	0	0
T114	29741	0	0	0
T115	13270	0	0	0
T116	73203	0	0	0
T149	0	4523	0	0
T170	0	40786	0	0
T174	0	2972	0	0
T196	0	2323	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457596318	456759280	0	0
T1	13524	13242	0	0
T2	93839	92927	0	0
T3	4148	4078	0	0
T4	13094	12852	0	0
T5	24791	24260	0	0
T6	28080	27618	0	0
T7	167250	167246	0	0
T10	23905	23659	0	0
T11	22899	22501	0	0
T12	9794	9732	0	0