Module Definition
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Module Instance : tb.dut.u_otp_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.68 100.00 94.74 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.83 100.00 92.31 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.19 94.16 96.15 97.02 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 95.00 89.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T7
110Not Covered
111CoveredT1,T2,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.68 94.74
tb.dut.u_otp_rsp_fifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

SCOREBRANCH
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 254989394 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1830385272 36644730 0 0
gen_passthru_fifo.paramCheckPass 7950 7950 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 254989394 0 0
T1 135240 8417 0 0
T2 938390 50158 0 0
T3 41480 1040 0 0
T4 130940 9707 0 0
T5 247910 16990 0 0
T6 280800 30878 0 0
T7 1672500 3539608 0 0
T10 239050 38311 0 0
T11 228990 24635 0 0
T12 97940 1236 0 0
T15 0 28282 0 0
T79 0 548 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 135240 132420 0 0
T2 938390 929270 0 0
T3 41480 40780 0 0
T4 130940 128520 0 0
T5 247910 242600 0 0
T6 280800 276180 0 0
T7 1672500 1672460 0 0
T10 239050 236590 0 0
T11 228990 225010 0 0
T12 97940 97320 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 135240 132420 0 0
T2 938390 929270 0 0
T3 41480 40780 0 0
T4 130940 128520 0 0
T5 247910 242600 0 0
T6 280800 276180 0 0
T7 1672500 1672460 0 0
T10 239050 236590 0 0
T11 228990 225010 0 0
T12 97940 97320 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 135240 132420 0 0
T2 938390 929270 0 0
T3 41480 40780 0 0
T4 130940 128520 0 0
T5 247910 242600 0 0
T6 280800 276180 0 0
T7 1672500 1672460 0 0
T10 239050 236590 0 0
T11 228990 225010 0 0
T12 97940 97320 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1830385272 36644730 0 0
T1 54096 3233 0 0
T2 375356 14618 0 0
T3 16592 936 0 0
T4 52376 3887 0 0
T5 99164 7994 0 0
T6 112320 7674 0 0
T7 669000 610356 0 0
T10 95620 2439 0 0
T11 91596 5027 0 0
T12 39176 936 0 0
T15 0 23725 0 0
T79 0 336 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 7950 7950 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T7 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T12 6 6 0 0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 457596318 16647365 0 0
DepthKnown_A 457596318 456759280 0 0
RvalidKnown_A 457596318 456759280 0 0
WreadyKnown_A 457596318 456759280 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 457596318 16647365 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 16647365 0 0
T1 13524 2787 0 0
T2 93839 13842 0 0
T3 4148 936 0 0
T4 13094 3488 0 0
T5 24791 7910 0 0
T6 28080 7191 0 0
T7 167250 98486 0 0
T10 23905 2166 0 0
T11 22899 4904 0 0
T12 9794 936 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 16647365 0 0
T1 13524 2787 0 0
T2 93839 13842 0 0
T3 4148 936 0 0
T4 13094 3488 0 0
T5 24791 7910 0 0
T6 28080 7191 0 0
T7 167250 98486 0 0
T10 23905 2166 0 0
T11 22899 4904 0 0
T12 9794 936 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 62752811 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 62752811 0 0
T1 13524 476 0 0
T2 93839 8841 0 0
T3 4148 26 0 0
T4 13094 1455 0 0
T5 24791 2249 0 0
T6 28080 5801 0 0
T7 167250 164021 0 0
T10 23905 8968 0 0
T11 22899 4902 0 0
T12 9794 75 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 51218744 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 51218744 0 0
T1 13524 2116 0 0
T2 93839 8929 0 0
T3 4148 26 0 0
T4 13094 1455 0 0
T5 24791 2249 0 0
T6 28080 5801 0 0
T7 167250 106362 0 0
T10 23905 8968 0 0
T11 22899 4902 0 0
T12 9794 75 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 26773602 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 26773602 0 0
T1 13524 16 0 0
T2 93839 56 0 0
T3 4148 0 0 0
T4 13094 19 0 0
T5 24791 4 0 0
T6 28080 23 0 0
T7 167250 999579 0 0
T10 23905 91 0 0
T11 22899 35 0 0
T12 9794 0 0 0
T15 0 959 0 0
T79 0 106 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 18602270 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 18602270 0 0
T1 13524 71 0 0
T2 93839 144 0 0
T3 4148 0 0 0
T4 13094 19 0 0
T5 24791 4 0 0
T6 28080 23 0 0
T7 167250 492177 0 0
T10 23905 91 0 0
T11 22899 35 0 0
T12 9794 0 0 0
T15 0 3598 0 0
T79 0 106 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 26380763 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 26380763 0 0
T1 13524 460 0 0
T2 93839 8785 0 0
T3 4148 26 0 0
T4 13094 1436 0 0
T5 24791 2245 0 0
T6 28080 5778 0 0
T7 167250 595661 0 0
T10 23905 8877 0 0
T11 22899 4867 0 0
T12 9794 75 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 460435408 32616474 0 0
DepthKnown_A 460435408 459547423 0 0
RvalidKnown_A 460435408 459547423 0 0
WreadyKnown_A 460435408 459547423 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 32616474 0 0
T1 13524 2045 0 0
T2 93839 8785 0 0
T3 4148 26 0 0
T4 13094 1436 0 0
T5 24791 2245 0 0
T6 28080 5778 0 0
T7 167250 571452 0 0
T10 23905 8877 0 0
T11 22899 4867 0 0
T12 9794 75 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460435408 459547423 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T4
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 457596318 19122527 0 0
DepthKnown_A 457596318 456759280 0 0
RvalidKnown_A 457596318 456759280 0 0
WreadyKnown_A 457596318 456759280 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 457596318 19122527 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 19122527 0 0
T1 13524 215 0 0
T2 93839 360 0 0
T3 4148 0 0 0
T4 13094 190 0 0
T5 24791 40 0 0
T6 28080 230 0 0
T7 167250 499611 0 0
T10 23905 91 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 11383 0 0
T79 0 115 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 19122527 0 0
T1 13524 215 0 0
T2 93839 360 0 0
T3 4148 0 0 0
T4 13094 190 0 0
T5 24791 40 0 0
T6 28080 230 0 0
T7 167250 499611 0 0
T10 23905 91 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 11383 0 0
T79 0 115 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T4
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 457596318 642851 0 0
DepthKnown_A 457596318 456759280 0 0
RvalidKnown_A 457596318 456759280 0 0
WreadyKnown_A 457596318 456759280 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 457596318 642851 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 642851 0 0
T1 13524 160 0 0
T2 93839 272 0 0
T3 4148 0 0 0
T4 13094 190 0 0
T5 24791 40 0 0
T6 28080 230 0 0
T7 167250 8592 0 0
T10 23905 91 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 8744 0 0
T79 0 115 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 642851 0 0
T1 13524 160 0 0
T2 93839 272 0 0
T3 4148 0 0 0
T4 13094 190 0 0
T5 24791 40 0 0
T6 28080 230 0 0
T7 167250 8592 0 0
T10 23905 91 0 0
T11 22899 44 0 0
T12 9794 0 0 0
T15 0 8744 0 0
T79 0 115 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T7
110Excluded VC_COV_UNR
111CoveredT1,T2,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 457596318 231987 0 0
DepthKnown_A 457596318 456759280 0 0
RvalidKnown_A 457596318 456759280 0 0
WreadyKnown_A 457596318 456759280 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 457596318 231987 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 231987 0 0
T1 13524 71 0 0
T2 93839 144 0 0
T3 4148 0 0 0
T4 13094 19 0 0
T5 24791 4 0 0
T6 28080 23 0 0
T7 167250 3667 0 0
T10 23905 91 0 0
T11 22899 35 0 0
T12 9794 0 0 0
T15 0 3598 0 0
T79 0 106 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 456759280 0 0
T1 13524 13242 0 0
T2 93839 92927 0 0
T3 4148 4078 0 0
T4 13094 12852 0 0
T5 24791 24260 0 0
T6 28080 27618 0 0
T7 167250 167246 0 0
T10 23905 23659 0 0
T11 22899 22501 0 0
T12 9794 9732 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 457596318 231987 0 0
T1 13524 71 0 0
T2 93839 144 0 0
T3 4148 0 0 0
T4 13094 19 0 0
T5 24791 4 0 0
T6 28080 23 0 0
T7 167250 3667 0 0
T10 23905 91 0 0
T11 22899 35 0 0
T12 9794 0 0 0
T15 0 3598 0 0
T79 0 106 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%