Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7396107 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 7357102 1 T1 5128 T2 1231 T3 672



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8529385 1 T1 10690 T2 2489 T3 5129
values[0x0] 2377488 1 T1 643 T2 140 T3 189
values[0x1] 3846336 1 T1 545 T2 133 T3 202



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4796937 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 9956272 1 T1 6621 T2 1574 T3 2186



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51101 1 T1 44 T2 16 T3 16
valid_sources[0x01] 61389 1 T1 38 T2 11 T3 25
valid_sources[0x02] 58850 1 T1 45 T2 5 T3 23
valid_sources[0x03] 54522 1 T1 53 T2 11 T3 39
valid_sources[0x04] 49541 1 T1 40 T2 20 T3 20
valid_sources[0x05] 52602 1 T1 44 T2 13 T3 20
valid_sources[0x06] 54382 1 T1 42 T2 12 T3 29
valid_sources[0x07] 63927 1 T1 51 T2 15 T3 21
valid_sources[0x08] 66205 1 T1 44 T2 13 T3 22
valid_sources[0x09] 55717 1 T1 53 T2 12 T3 20
valid_sources[0x0a] 61573 1 T1 51 T2 9 T3 14
valid_sources[0x0b] 56508 1 T1 39 T2 13 T3 15
valid_sources[0x0c] 52424 1 T1 48 T2 8 T3 20
valid_sources[0x0d] 59119 1 T1 51 T2 13 T3 27
valid_sources[0x0e] 65068 1 T1 50 T2 15 T3 24
valid_sources[0x0f] 55602 1 T1 43 T2 7 T3 19
valid_sources[0x10] 53024 1 T1 34 T2 6 T3 21
valid_sources[0x11] 56025 1 T1 57 T2 12 T3 23
valid_sources[0x12] 54264 1 T1 46 T2 21 T3 17
valid_sources[0x13] 53431 1 T1 55 T2 12 T3 18
valid_sources[0x14] 51237 1 T1 46 T2 9 T3 21
valid_sources[0x15] 61271 1 T1 34 T2 13 T3 19
valid_sources[0x16] 52563 1 T1 51 T2 10 T3 27
valid_sources[0x17] 62555 1 T1 49 T2 12 T3 19
valid_sources[0x18] 56714 1 T1 47 T2 10 T3 16
valid_sources[0x19] 53723 1 T1 47 T2 4 T3 24
valid_sources[0x1a] 60946 1 T1 49 T2 8 T3 20
valid_sources[0x1b] 66205 1 T1 40 T2 15 T3 20
valid_sources[0x1c] 53200 1 T1 33 T2 16 T3 18
valid_sources[0x1d] 51985 1 T1 40 T2 4 T3 40
valid_sources[0x1e] 52604 1 T1 48 T2 9 T3 19
valid_sources[0x1f] 50662 1 T1 50 T2 7 T3 29
valid_sources[0x20] 60039 1 T1 40 T2 11 T3 22
valid_sources[0x21] 57118 1 T1 65 T2 9 T3 14
valid_sources[0x22] 50108 1 T1 43 T2 11 T3 29
valid_sources[0x23] 53969 1 T1 32 T2 10 T3 18
valid_sources[0x24] 56574 1 T1 44 T2 15 T3 15
valid_sources[0x25] 67389 1 T1 58 T2 5 T3 31
valid_sources[0x26] 65574 1 T1 37 T2 9 T3 24
valid_sources[0x27] 62385 1 T1 36 T2 16 T3 18
valid_sources[0x28] 58966 1 T1 42 T2 14 T3 26
valid_sources[0x29] 51516 1 T1 40 T2 7 T3 30
valid_sources[0x2a] 53909 1 T1 44 T2 8 T3 25
valid_sources[0x2b] 63868 1 T1 48 T2 13 T3 22
valid_sources[0x2c] 51890 1 T1 50 T2 15 T3 27
valid_sources[0x2d] 55572 1 T1 42 T2 11 T3 17
valid_sources[0x2e] 56789 1 T1 42 T2 10 T3 24
valid_sources[0x2f] 50576 1 T1 48 T2 9 T3 23
valid_sources[0x30] 56620 1 T1 53 T2 5 T3 24
valid_sources[0x31] 99982 1 T1 45 T2 4 T3 14
valid_sources[0x32] 55622 1 T1 47 T2 10 T3 13
valid_sources[0x33] 67694 1 T1 52 T2 20 T3 15
valid_sources[0x34] 69699 1 T1 39 T2 8 T3 21
valid_sources[0x35] 55122 1 T1 38 T2 9 T3 27
valid_sources[0x36] 52403 1 T1 41 T2 10 T3 15
valid_sources[0x37] 52228 1 T1 55 T2 10 T3 21
valid_sources[0x38] 51429 1 T1 37 T2 13 T3 16
valid_sources[0x39] 52205 1 T1 56 T2 9 T3 24
valid_sources[0x3a] 51653 1 T1 47 T2 9 T3 18
valid_sources[0x3b] 51478 1 T1 39 T2 7 T3 16
valid_sources[0x3c] 57446 1 T1 66 T2 8 T3 20
valid_sources[0x3d] 53104 1 T1 43 T2 8 T3 23
valid_sources[0x3e] 52002 1 T1 54 T2 6 T3 39
valid_sources[0x3f] 54335 1 T1 39 T2 10 T3 22
valid_sources[0x40] 52478 1 T1 37 T2 8 T3 15
valid_sources[0x41] 55741 1 T1 57 T2 8 T3 23
valid_sources[0x42] 50745 1 T1 39 T2 6 T3 28
valid_sources[0x43] 55993 1 T1 35 T2 10 T3 20
valid_sources[0x44] 51662 1 T1 54 T2 16 T3 39
valid_sources[0x45] 56046 1 T1 42 T2 10 T3 31
valid_sources[0x46] 51410 1 T1 41 T2 11 T3 21
valid_sources[0x47] 52422 1 T1 40 T2 16 T3 17
valid_sources[0x48] 55102 1 T1 51 T2 10 T3 16
valid_sources[0x49] 60221 1 T1 49 T2 9 T3 16
valid_sources[0x4a] 50975 1 T1 47 T2 13 T3 24
valid_sources[0x4b] 53325 1 T1 51 T2 10 T3 13
valid_sources[0x4c] 54625 1 T1 55 T2 18 T3 19
valid_sources[0x4d] 52064 1 T1 53 T2 7 T3 27
valid_sources[0x4e] 54129 1 T1 56 T2 5 T3 13
valid_sources[0x4f] 56660 1 T1 53 T2 16 T3 28
valid_sources[0x50] 50485 1 T1 48 T2 11 T3 17
valid_sources[0x51] 56478 1 T1 52 T2 12 T3 24
valid_sources[0x52] 65841 1 T1 48 T2 15 T3 19
valid_sources[0x53] 62548 1 T1 54 T2 15 T3 21
valid_sources[0x54] 57100 1 T1 58 T2 12 T3 22
valid_sources[0x55] 61343 1 T1 46 T2 9 T3 12
valid_sources[0x56] 55078 1 T1 37 T2 12 T3 19
valid_sources[0x57] 52343 1 T1 50 T2 7 T3 23
valid_sources[0x58] 56239 1 T1 40 T2 11 T3 24
valid_sources[0x59] 55276 1 T1 42 T2 6 T3 19
valid_sources[0x5a] 52883 1 T1 53 T2 15 T3 17
valid_sources[0x5b] 52253 1 T1 43 T2 8 T3 20
valid_sources[0x5c] 54066 1 T1 36 T2 7 T3 28
valid_sources[0x5d] 52625 1 T1 35 T2 12 T3 23
valid_sources[0x5e] 53751 1 T1 37 T2 5 T3 18
valid_sources[0x5f] 54042 1 T1 62 T2 15 T3 18
valid_sources[0x60] 65911 1 T1 50 T2 6 T3 22
valid_sources[0x61] 64229 1 T1 46 T2 5 T3 14
valid_sources[0x62] 61648 1 T1 52 T2 14 T3 33
valid_sources[0x63] 50344 1 T1 51 T2 11 T3 26
valid_sources[0x64] 68661 1 T1 54 T2 19 T3 29
valid_sources[0x65] 54873 1 T1 29 T2 7 T3 12
valid_sources[0x66] 55032 1 T1 56 T2 11 T3 22
valid_sources[0x67] 56398 1 T1 42 T2 9 T3 26
valid_sources[0x68] 54360 1 T1 53 T2 9 T3 30
valid_sources[0x69] 52983 1 T1 39 T2 9 T3 25
valid_sources[0x6a] 54755 1 T1 39 T2 10 T3 21
valid_sources[0x6b] 60457 1 T1 35 T2 10 T3 23
valid_sources[0x6c] 52237 1 T1 43 T2 10 T3 13
valid_sources[0x6d] 52009 1 T1 56 T2 10 T3 30
valid_sources[0x6e] 51789 1 T1 42 T2 14 T3 15
valid_sources[0x6f] 58410 1 T1 49 T2 6 T3 24
valid_sources[0x70] 56840 1 T1 35 T2 21 T3 15
valid_sources[0x71] 52428 1 T1 47 T2 14 T3 24
valid_sources[0x72] 52115 1 T1 52 T2 8 T3 23
valid_sources[0x73] 52907 1 T1 45 T2 15 T3 24
valid_sources[0x74] 67611 1 T1 45 T2 8 T3 21
valid_sources[0x75] 51201 1 T1 41 T2 14 T3 20
valid_sources[0x76] 62136 1 T1 44 T2 16 T3 29
valid_sources[0x77] 55834 1 T1 43 T2 11 T3 21
valid_sources[0x78] 51604 1 T1 36 T2 9 T3 25
valid_sources[0x79] 51283 1 T1 50 T2 15 T3 17
valid_sources[0x7a] 56724 1 T1 49 T2 14 T3 27
valid_sources[0x7b] 54439 1 T1 48 T2 14 T3 16
valid_sources[0x7c] 60913 1 T1 43 T2 13 T3 22
valid_sources[0x7d] 50448 1 T1 42 T2 7 T3 27
valid_sources[0x7e] 51602 1 T1 54 T2 8 T3 21
valid_sources[0x7f] 56161 1 T1 39 T2 13 T3 17
valid_sources[0x80] 51210 1 T1 63 T2 12 T3 18



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3494951 1 T1 4675 T2 1121 T3 512
values[0x0] all_enables biggest_size 1971917 1 T1 306 T2 65 T3 85
values[0x1] all_enables biggest_size 1890234 1 T1 147 T2 45 T3 75


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 252316 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 9147024 1 T1 160 T2 100 T3 160



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 2338026 1 T1 80 T2 50 T3 80
values[0x0] 3426626 1 T1 36 T2 29 T3 36
values[0x1] 3634688 1 T1 44 T2 21 T3 44



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 90618 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 9308722 1 T1 160 T2 100 T3 160



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 37378 1 T5 8 T10 1 T6 220
valid_sources[0x01] 37880 1 T4 1 T5 5 T6 265
valid_sources[0x02] 35857 1 T5 18 T10 1 T6 283
valid_sources[0x03] 36779 1 T10 1 T6 228 T36 1
valid_sources[0x04] 37742 1 T10 2 T6 281 T36 1
valid_sources[0x05] 36089 1 T4 1 T5 6 T6 238
valid_sources[0x06] 35928 1 T6 230 T74 1 T7 631
valid_sources[0x07] 35149 1 T6 251 T74 1 T166 1
valid_sources[0x08] 37311 1 T4 1 T5 1 T10 4
valid_sources[0x09] 37084 1 T6 246 T7 628 T8 3
valid_sources[0x0a] 36940 1 T4 1 T5 1 T6 239
valid_sources[0x0b] 35759 1 T5 3 T10 3 T6 234
valid_sources[0x0c] 37957 1 T10 3 T6 249 T7 708
valid_sources[0x0d] 38393 1 T10 1 T6 245 T36 1
valid_sources[0x0e] 36479 1 T5 1 T6 259 T96 4
valid_sources[0x0f] 36866 1 T5 1 T10 1 T6 247
valid_sources[0x10] 34814 1 T5 1 T6 272 T36 1
valid_sources[0x11] 37373 1 T4 1 T10 2 T6 243
valid_sources[0x12] 37168 1 T2 36 T4 1 T5 1
valid_sources[0x13] 36628 1 T5 5 T6 219 T98 1
valid_sources[0x14] 37166 1 T6 246 T98 2 T96 4
valid_sources[0x15] 37257 1 T5 4 T6 247 T74 2
valid_sources[0x16] 37622 1 T5 10 T6 263 T98 2
valid_sources[0x17] 36300 1 T5 8 T6 259 T63 1
valid_sources[0x18] 36812 1 T6 254 T36 1 T204 1
valid_sources[0x19] 38002 1 T2 6 T10 1 T6 240
valid_sources[0x1a] 36804 1 T5 6 T6 278 T36 1
valid_sources[0x1b] 36560 1 T4 1 T5 3 T6 262
valid_sources[0x1c] 37088 1 T6 239 T98 2 T36 1
valid_sources[0x1d] 36669 1 T5 2 T6 270 T36 1
valid_sources[0x1e] 36811 1 T4 1 T6 269 T36 3
valid_sources[0x1f] 36955 1 T4 1 T6 237 T7 641
valid_sources[0x20] 36165 1 T5 2 T6 272 T7 644
valid_sources[0x21] 36969 1 T4 1 T5 1 T6 246
valid_sources[0x22] 37117 1 T5 5 T6 239 T36 3
valid_sources[0x23] 36456 1 T5 4 T10 1 T6 249
valid_sources[0x24] 37277 1 T5 3 T6 249 T74 3
valid_sources[0x25] 36621 1 T5 7 T10 2 T6 240
valid_sources[0x26] 36039 1 T5 2 T10 2 T6 237
valid_sources[0x27] 35670 1 T5 3 T6 261 T36 2
valid_sources[0x28] 37177 1 T10 2 T6 247 T123 3
valid_sources[0x29] 36998 1 T5 3 T6 256 T7 696
valid_sources[0x2a] 36979 1 T6 247 T96 1 T165 1
valid_sources[0x2b] 36603 1 T6 246 T36 1 T166 1
valid_sources[0x2c] 36931 1 T5 3 T10 2 T6 253
valid_sources[0x2d] 36883 1 T5 3 T10 2 T6 277
valid_sources[0x2e] 36012 1 T4 1 T5 1 T6 231
valid_sources[0x2f] 37103 1 T6 248 T166 2 T7 611
valid_sources[0x30] 35533 1 T5 4 T6 247 T36 1
valid_sources[0x31] 35653 1 T4 1 T10 2 T6 260
valid_sources[0x32] 36561 1 T5 5 T10 3 T6 213
valid_sources[0x33] 34930 1 T4 1 T6 240 T36 2
valid_sources[0x34] 37240 1 T10 2 T6 225 T36 3
valid_sources[0x35] 35553 1 T6 257 T123 6 T74 1
valid_sources[0x36] 35388 1 T10 5 T6 237 T98 6
valid_sources[0x37] 36848 1 T10 2 T6 290 T36 1
valid_sources[0x38] 37334 1 T4 2 T5 4 T10 1
valid_sources[0x39] 38107 1 T10 3 T6 228 T166 1
valid_sources[0x3a] 36147 1 T10 3 T6 244 T36 2
valid_sources[0x3b] 36211 1 T4 1 T10 2 T6 240
valid_sources[0x3c] 35934 1 T5 2 T10 3 T6 268
valid_sources[0x3d] 37095 1 T4 1 T6 252 T36 1
valid_sources[0x3e] 37143 1 T6 241 T36 1 T74 1
valid_sources[0x3f] 37809 1 T4 1 T5 1 T6 253
valid_sources[0x40] 36982 1 T5 1 T6 262 T63 10
valid_sources[0x41] 37632 1 T4 2 T5 1 T10 1
valid_sources[0x42] 36670 1 T4 2 T6 233 T98 1
valid_sources[0x43] 36701 1 T4 2 T6 212 T36 1
valid_sources[0x44] 36916 1 T5 2 T6 248 T96 2
valid_sources[0x45] 37468 1 T5 6 T10 4 T6 253
valid_sources[0x46] 37407 1 T4 1 T10 1 T6 241
valid_sources[0x47] 37312 1 T5 3 T6 229 T166 1
valid_sources[0x48] 36284 1 T5 1 T6 254 T36 1
valid_sources[0x49] 37153 1 T5 5 T6 252 T7 634
valid_sources[0x4a] 37229 1 T10 1 T6 257 T36 2
valid_sources[0x4b] 37429 1 T10 2 T6 224 T7 700
valid_sources[0x4c] 36385 1 T5 1 T10 2 T6 269
valid_sources[0x4d] 36731 1 T6 224 T36 1 T74 1
valid_sources[0x4e] 35605 1 T6 257 T36 1 T166 1
valid_sources[0x4f] 37018 1 T4 1 T5 10 T10 1
valid_sources[0x50] 36705 1 T5 5 T6 242 T36 1
valid_sources[0x51] 35985 1 T10 2 T6 233 T7 653
valid_sources[0x52] 38151 1 T6 236 T36 1 T7 670
valid_sources[0x53] 36323 1 T5 9 T6 258 T63 2
valid_sources[0x54] 36958 1 T5 8 T6 226 T98 1
valid_sources[0x55] 36701 1 T5 5 T6 223 T36 1
valid_sources[0x56] 36455 1 T5 17 T10 1 T6 243
valid_sources[0x57] 37752 1 T6 233 T96 1 T74 1
valid_sources[0x58] 37419 1 T5 16 T10 3 T6 280
valid_sources[0x59] 36118 1 T5 4 T6 251 T98 1
valid_sources[0x5a] 37684 1 T4 1 T5 1 T10 3
valid_sources[0x5b] 37169 1 T6 267 T7 683 T129 1
valid_sources[0x5c] 37697 1 T5 1 T6 217 T96 3
valid_sources[0x5d] 36431 1 T5 1 T6 255 T98 1
valid_sources[0x5e] 35500 1 T5 1 T6 241 T96 2
valid_sources[0x5f] 36285 1 T5 2 T10 2 T6 249
valid_sources[0x60] 35155 1 T6 299 T63 8 T96 3
valid_sources[0x61] 36427 1 T6 269 T7 663 T8 2
valid_sources[0x62] 36827 1 T6 257 T74 1 T166 2
valid_sources[0x63] 36837 1 T5 3 T6 263 T96 3
valid_sources[0x64] 36032 1 T4 1 T5 1 T6 255
valid_sources[0x65] 37387 1 T4 1 T5 3 T6 226
valid_sources[0x66] 38262 1 T5 13 T10 2 T6 251
valid_sources[0x67] 36467 1 T5 1 T6 235 T36 2
valid_sources[0x68] 35868 1 T5 7 T10 1 T6 233
valid_sources[0x69] 35443 1 T5 1 T6 252 T7 674
valid_sources[0x6a] 36259 1 T5 11 T6 237 T96 1
valid_sources[0x6b] 35908 1 T6 286 T36 2 T96 2
valid_sources[0x6c] 35234 1 T1 160 T4 1 T10 1
valid_sources[0x6d] 36792 1 T6 251 T98 1 T166 1
valid_sources[0x6e] 37871 1 T4 1 T6 227 T36 1
valid_sources[0x6f] 36626 1 T5 7 T6 229 T63 1
valid_sources[0x70] 37036 1 T10 1 T6 240 T36 2
valid_sources[0x71] 36863 1 T6 237 T96 2 T74 1
valid_sources[0x72] 36873 1 T4 2 T5 5 T10 2
valid_sources[0x73] 37729 1 T4 1 T6 251 T36 1
valid_sources[0x74] 35428 1 T4 2 T6 225 T7 607
valid_sources[0x75] 36766 1 T10 2 T6 248 T95 200
valid_sources[0x76] 36158 1 T6 241 T12 19 T96 1
valid_sources[0x77] 36576 1 T5 3 T6 256 T36 3
valid_sources[0x78] 36347 1 T5 5 T10 3 T6 260
valid_sources[0x79] 36724 1 T4 1 T10 1 T6 249
valid_sources[0x7a] 36535 1 T4 1 T5 2 T10 1
valid_sources[0x7b] 38582 1 T5 7 T6 252 T96 1
valid_sources[0x7c] 36797 1 T5 2 T6 277 T172 1
valid_sources[0x7d] 37162 1 T5 5 T10 4 T6 222
valid_sources[0x7e] 36138 1 T6 250 T98 3 T63 9
valid_sources[0x7f] 36771 1 T5 1 T6 233 T166 1
valid_sources[0x80] 37386 1 T5 4 T6 255 T63 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2325078 1 T1 80 T2 50 T3 80
values[0x0] all_enables biggest_size 3409435 1 T1 36 T2 29 T3 36
values[0x1] all_enables biggest_size 3412511 1 T1 44 T2 21 T3 44

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