SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21445717 | 1 | T1 | 11779 | T2 | 2738 | T3 | 5493 | ||||
auto[1] | 12764297 | 1 | T1 | 99 | T2 | 24 | T3 | 27 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34209813 | 1 | T1 | 11878 | T2 | 2762 | T3 | 5520 | ||||
values[1] | 18 | 1 | T258 | 1 | T340 | 1 | T341 | 4 | ||||
values[2] | 9 | 1 | T251 | 1 | T258 | 1 | T342 | 1 | ||||
values[3] | 114 | 1 | T251 | 5 | T252 | 4 | T253 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34209810 | 1 | T1 | 11878 | T2 | 2762 | T3 | 5520 | ||||
values[1] | 25 | 1 | T251 | 1 | T252 | 2 | T253 | 2 | ||||
values[2] | 4 | 1 | T341 | 1 | T343 | 1 | T256 | 1 | ||||
values[3] | 105 | 1 | T251 | 3 | T252 | 5 | T253 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34209714 | 1 | T1 | 11878 | T2 | 2762 | T3 | 5520 | ||||
auto[TlIntgErrCmd] | 96 | 1 | T251 | 6 | T253 | 4 | T258 | 2 | ||||
auto[TlIntgErrData] | 99 | 1 | T251 | 9 | T252 | 5 | T253 | 5 | ||||
auto[TlIntgErrBoth] | 105 | 1 | T251 | 5 | T252 | 5 | T253 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 4112414 | 0 | T1 | 124 | T5 | 214 | T6 | 39398 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4112224 | 1 | T1 | 124 | T5 | 214 | T6 | 39398 | ||||
values[1] | 18 | 1 | T251 | 1 | T252 | 2 | T340 | 2 | ||||
values[2] | 5 | 1 | T251 | 2 | T256 | 1 | T344 | 1 | ||||
values[3] | 94 | 1 | T251 | 8 | T252 | 1 | T253 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4112200 | 1 | T1 | 124 | T5 | 214 | T6 | 39398 | ||||
values[1] | 31 | 1 | T251 | 2 | T252 | 1 | T253 | 1 | ||||
values[2] | 7 | 1 | T341 | 1 | T343 | 1 | T345 | 1 | ||||
values[3] | 95 | 1 | T251 | 9 | T252 | 5 | T253 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4112114 | 1 | T1 | 124 | T5 | 214 | T6 | 39398 | ||||
auto[TlIntgErrCmd] | 86 | 1 | T251 | 5 | T252 | 1 | T253 | 2 | ||||
auto[TlIntgErrData] | 110 | 1 | T251 | 6 | T252 | 7 | T253 | 5 | ||||
auto[TlIntgErrBoth] | 104 | 1 | T251 | 9 | T252 | 2 | T253 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |