Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25741350

1

T1

6750

T2

1531

T3

4848

full_word

8468664

1

T1

5128

T2

1231

T3

672

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34209714	1			T1	11878		T2	2762		T3	5520
auto[TlIntgErrCmd]	96	1			T251	6		T253	4		T258	2
auto[TlIntgErrData]	99	1			T251	9		T252	5		T253	5
auto[TlIntgErrBoth]	105	1			T251	5		T252	5		T253	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9876582

1

T1

10690

T2

2489

T3

5129

auto[1]

24333432

1

T1

1188

T2

273

T3

391

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6244976	1			T1	6015		T2	1368		T3	4617
auto[TlIntgErrNone]	partial	auto[1]	19496103	1			T1	735		T2	163		T3	231
auto[TlIntgErrNone]	full_word	auto[0]	3631478	1			T1	4675		T2	1121		T3	512
auto[TlIntgErrNone]	full_word	auto[1]	4837157	1			T1	453		T2	110		T3	160
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T251	1		T253	4		T258	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T251	5		T258	1		T340	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T256	1		T346	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T341	1		T256	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T251	2		T252	2		T258	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T251	7		T252	3		T253	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T253	1		T340	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T253	1		T341	1		T343	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T252	2		T340	1		T341	6
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T251	4		T252	2		T253	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T346	1		T348	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T251	1		T252	1		T258	2