Unified Coverage Report :: Module :: otp_ctrl_lci

Module : otp_ctrl_lci

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lci	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lci

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
TOTAL		52	52	100.00
CONT_ASSIGN	114	1	1	100.00
ALWAYS	117	41	41	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	274	3	3	100.00
ALWAYS	277	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
114	1	1
117	1	1
120	1	1
121	1	1
124	1	1
127	1	1
128	1	1
131	1	1
132	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
172	1	1
173	1	1
179	1	1
180	1	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
			MISSING_ELSE
196	1	1
197	1	1
			MISSING_ELSE
206	1	1
207	1	1
			MISSING_ELSE
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
			MISSING_ELSE
258	1	1
264	1	1
265	1	1
268	1	1
274	3	3
277	1	1
278	1	1
280	1	1

---

Cond Coverage for Module : otp_ctrl_lci

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       179
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T13,T18

 LINE       185
 EXPRESSION (cnt == LastLcOtpWord)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       190
 EXPRESSION (error_d != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T13,T18

 LINE       206
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T9,T5
1	Covered	T21,T22,T23

 LINE       225
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T9,T5
1	Covered	T2,T9,T5

 LINE       265
 EXPRESSION (otp_req_o ? (64'(data[cnt])) : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Module : otp_ctrl_lci

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	192	Covered	T2,T9,T5
IdleSt	144	Covered	T1,T2,T3
ResetSt	141	Covered	T1,T2,T3
WriteSt	151	Covered	T1,T3,T4
WriteWaitSt	164	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	223	Covered	T2,T5,T10
IdleSt->WriteSt	151	Covered	T1,T3,T4
ResetSt->ErrorSt	223	Covered	T9,T11,T64
ResetSt->IdleSt	144	Covered	T1,T2,T3
WriteSt->ErrorSt	223	Covered	T8,T317,T274
WriteSt->WriteWaitSt	164	Covered	T1,T3,T4
WriteWaitSt->ErrorSt	192	Covered	T8,T173,T14
WriteWaitSt->IdleSt	186	Covered	T1,T3,T4
WriteWaitSt->WriteSt	196	Covered	T1,T3,T4

---

Branch Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	265	2	2	100.00
CASE	138	15	15	100.00
IF	222	3	3	100.00
IF	274	2	2	100.00
IF	277	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	265	(otp_req_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	143	if (lci_en_i)
-3-:	150	if (lc_req_i)
-4-:	163	if (otp_gnt_i)
-5-:	173	if (otp_rvalid_i)
-6-:	179	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	185	if ((cnt == LastLcOtpWord))
-8-:	190	if ((error_d != NoError))
-9-:	206	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	1	-	-	-	-	-	Covered	T1,T3,T4
WriteSt	-	-	0	-	-	-	-	-	Covered	T3,T4,T12
WriteWaitSt	-	-	-	1	1	-	-	-	Covered	T14,T13,T18
WriteWaitSt	-	-	-	1	0	-	-	-	Covered	T1,T3,T4
WriteWaitSt	-	-	-	1	-	1	1	-	Covered	T14,T13,T18
WriteWaitSt	-	-	-	1	-	1	0	-	Covered	T1,T3,T4
WriteWaitSt	-	-	-	1	-	0	-	-	Covered	T1,T3,T4
WriteWaitSt	-	-	-	0	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	1	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	0	Covered	T2,T9,T5
default	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	222	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	225	if ((error_q == NoError))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T9,T5
1	0	Covered	T2,T9,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	277	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_lci

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorKnown_A	477811149	476919687	0	0
LcAckKnown_A	477811149	476919687	0	0
LcErrKnown_A	477811149	476919687	0	0
LcValueMustBeWiderThanNativeOtpWidth_A	1152	1152	0	0
LciIdleKnown_A	477811149	476919687	0	0
OtpAddrKnown_A	477811149	476919687	0	0
OtpCmdKnown_A	477811149	476919687	0	0
OtpReqKnown_A	477811149	476919687	0	0
OtpSizeKnown_A	477811149	476919687	0	0
OtpWdataKnown_A	477811149	476919687	0	0
u_state_regs_A	477811149	476919687	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

LcAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

LcErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

LcValueMustBeWiderThanNativeOtpWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

LciIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477811149	476919687	0	0
T1	128331	127230	0	0
T2	38254	37952	0	0
T3	58595	57411	0	0
T4	27731	26958	0	0
T5	418093	413398	0	0
T6	347169	347156	0	0
T9	13275	12990	0	0
T10	18025	17832	0	0
T11	12680	12419	0	0
T12	72101	70547	0	0