Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	480823060	8269820	0	0
check_regwen_rd_A	480823060	1902	0	0
check_timeout_rd_A	480823060	1866	0	0
check_trigger_regwen_rd_A	480823060	1967	0	0
consistency_check_period_rd_A	480823060	2099	0	0
creator_sw_cfg_read_lock_rd_A	480823060	1962	0	0
direct_access_address_rd_A	480823060	1710	0	0
direct_access_wdata_0_rd_A	480823060	1146	0	0
direct_access_wdata_1_rd_A	480823060	1252	0	0
integrity_check_period_rd_A	480823060	1920	0	0
intr_enable_rd_A	480823060	2764	0	0
owner_sw_cfg_read_lock_rd_A	480823060	1618	0	0
rot_creator_auth_codesign_read_lock_rd_A	480823060	1671	0	0
rot_creator_auth_state_read_lock_rd_A	480823060	1676	0	0
vendor_test_read_lock_rd_A	480823060	1938	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	8269820	0	0
T6	347169	56928	0	0
T7	0	142384	0	0
T12	72101	0	0	0
T13	0	191676	0	0
T16	0	80593	0	0
T17	0	216573	0	0
T18	0	146487	0	0
T19	0	48554	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T244	0	90827	0	0
T260	0	158528	0	0
T261	0	64377	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1902	0	0
T6	347169	48	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	67	0	0
T244	0	76	0	0
T245	0	13	0	0
T269	0	82	0	0
T285	0	38	0	0
T318	0	99	0	0
T319	0	148	0	0
T320	0	52	0	0
T321	0	109	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1866	0	0
T6	347169	40	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	49	0	0
T244	0	88	0	0
T245	0	9	0	0
T269	0	119	0	0
T285	0	122	0	0
T318	0	89	0	0
T319	0	90	0	0
T320	0	61	0	0
T321	0	103	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1967	0	0
T6	347169	74	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	72	0	0
T244	0	36	0	0
T245	0	6	0	0
T269	0	122	0	0
T285	0	70	0	0
T318	0	47	0	0
T319	0	119	0	0
T320	0	90	0	0
T321	0	74	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	2099	0	0
T6	347169	54	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	85	0	0
T244	0	59	0	0
T245	0	11	0	0
T269	0	86	0	0
T285	0	71	0	0
T318	0	91	0	0
T319	0	114	0	0
T320	0	83	0	0
T321	0	123	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1962	0	0
T6	347169	38	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	88	0	0
T244	0	77	0	0
T245	0	18	0	0
T269	0	140	0	0
T285	0	108	0	0
T318	0	80	0	0
T319	0	208	0	0
T320	0	59	0	0
T321	0	103	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1710	0	0
T6	347169	21	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	77	0	0
T244	0	69	0	0
T245	0	15	0	0
T269	0	103	0	0
T285	0	73	0	0
T318	0	98	0	0
T319	0	118	0	0
T320	0	71	0	0
T321	0	100	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1146	0	0
T6	347169	23	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	73	0	0
T244	0	60	0	0
T269	0	46	0	0
T285	0	73	0	0
T318	0	37	0	0
T319	0	106	0	0
T320	0	77	0	0
T321	0	80	0	0
T322	0	100	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1252	0	0
T6	347169	41	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	64	0	0
T244	0	56	0	0
T269	0	81	0	0
T285	0	83	0	0
T318	0	43	0	0
T319	0	106	0	0
T320	0	50	0	0
T321	0	96	0	0
T322	0	130	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1920	0	0
T6	347169	38	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	61	0	0
T244	0	59	0	0
T245	0	8	0	0
T269	0	146	0	0
T285	0	110	0	0
T318	0	62	0	0
T319	0	91	0	0
T320	0	53	0	0
T321	0	94	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	2764	0	0
T6	347169	91	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	83	0	0
T213	0	16	0	0
T244	0	83	0	0
T245	0	5	0	0
T269	0	80	0	0
T285	0	82	0	0
T318	0	44	0	0
T319	0	100	0	0
T323	0	24	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1618	0	0
T6	347169	67	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	71	0	0
T244	0	35	0	0
T245	0	6	0	0
T269	0	121	0	0
T285	0	100	0	0
T318	0	70	0	0
T319	0	126	0	0
T320	0	31	0	0
T321	0	73	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1671	0	0
T6	347169	48	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	46	0	0
T244	0	54	0	0
T245	0	15	0	0
T269	0	88	0	0
T285	0	69	0	0
T318	0	94	0	0
T319	0	104	0	0
T320	0	106	0	0
T321	0	98	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1676	0	0
T6	347169	54	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	57	0	0
T244	0	85	0	0
T245	0	8	0	0
T269	0	105	0	0
T285	0	68	0	0
T318	0	93	0	0
T319	0	137	0	0
T320	0	63	0	0
T321	0	96	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480823060	1938	0	0
T6	347169	45	0	0
T12	72101	0	0	0
T36	142987	0	0	0
T47	11017	0	0	0
T63	50282	0	0	0
T64	10172	0	0	0
T95	71046	0	0	0
T98	20046	0	0	0
T100	148387	0	0	0
T105	9499	0	0	0
T137	0	64	0	0
T244	0	50	0	0
T245	0	14	0	0
T269	0	134	0	0
T285	0	101	0	0
T318	0	109	0	0
T319	0	135	0	0
T320	0	114	0	0
T321	0	126	0	0