SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sender_otp_broadcast_valid | 100.00 | 100.00 | |||||
tb.dut.u_prim_lc_sender_test_tokens_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sender_rma_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sender_secrets_valid | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.17 | 94.16 | 96.15 | 96.94 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.17 | 94.16 | 96.15 | 96.94 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_no_flops.gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.17 | 94.16 | 96.15 | 96.94 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_no_flops.gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.17 | 94.16 | 96.15 | 96.94 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_no_flops.gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_no_flops.gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
66 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
58 | 1 | 1 | |
59 | 1 | 1 | |
61 | 1 | 1 | |
66 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 2 | 2 | 100.00 | |
IF | 58 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 58 if ((!rst_ni))
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
66 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
58 | 1 | 1 | |
59 | 1 | 1 | |
61 | 1 | 1 | |
66 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 2 | 2 | 100.00 | |
IF | 58 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 58 if ((!rst_ni))
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
58 | 1 | 1 | |
59 | 1 | 1 | |
61 | 1 | 1 | |
66 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 2 | 2 | 100.00 | |
IF | 58 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 58 if ((!rst_ni))
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
58 | 1 | 1 | |
59 | 1 | 1 | |
61 | 1 | 1 | |
66 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 2 | 2 | 100.00 | |
IF | 58 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 58 if ((!rst_ni))
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |