Module Definition
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Module : prim_sync_reqack_data
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_prim_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 95.83 100.00 83.33 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 477811149 564820 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 477811149 564762 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 477811149 564820 0 0
T1 128331 664 0 0
T2 38254 0 0 0
T3 58595 1106 0 0
T4 27731 0 0 0
T5 418093 3111 0 0
T6 347169 858 0 0
T9 13275 0 0 0
T10 18025 0 0 0
T11 12680 0 0 0
T12 72101 978 0 0
T36 0 762 0 0
T63 0 378 0 0
T95 0 566 0 0
T98 0 290 0 0
T100 0 544 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 477811149 564762 0 0
T1 128331 664 0 0
T2 38254 0 0 0
T3 58595 1106 0 0
T4 27731 0 0 0
T5 418093 3111 0 0
T6 347169 858 0 0
T9 13275 0 0 0
T10 18025 0 0 0
T11 12680 0 0 0
T12 72101 978 0 0
T36 0 762 0 0
T63 0 378 0 0
T95 0 566 0 0
T98 0 290 0 0
T100 0 544 0 0

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