Line Coverage for Instance : tb.dut.u_scrmbl_mtx
| Line No. | Total | Covered | Percent |
TOTAL | | 192 | 144 | 75.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 0 | 0 | |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 0 | 0 | |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
7 |
14 |
118 |
14 |
14 |
122 |
7 |
14 |
126 |
|
unreachable |
128 |
14 |
14 |
138 |
2 |
2 |
148 |
11 |
14(1 unreachable) |
150 |
11 |
14(1 unreachable) |
151 |
11 |
14(1 unreachable) |
155 |
8 |
15 |
156 |
11 |
15 |
160 |
11 |
14(1 unreachable) |
161 |
12 |
15 |
163 |
8 |
11(4 unreachable) |
164 |
10 |
15 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_scrmbl_mtx
| Total | Covered | Percent |
Conditions | 362 | 360 | 99.45 |
Logical | 362 | 360 | 99.45 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_scrmbl_mtx
| Line No. | Total | Covered | Percent |
Branches |
|
74 |
74 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
155 |
1 |
1 |
100.00 |
TERNARY |
156 |
1 |
1 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_scrmbl_mtx
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
476919687 |
0 |
0 |
T1 |
128331 |
127230 |
0 |
0 |
T2 |
38254 |
37952 |
0 |
0 |
T3 |
58595 |
57411 |
0 |
0 |
T4 |
27731 |
26958 |
0 |
0 |
T5 |
418093 |
413398 |
0 |
0 |
T6 |
347169 |
347156 |
0 |
0 |
T9 |
13275 |
12990 |
0 |
0 |
T10 |
18025 |
17832 |
0 |
0 |
T11 |
12680 |
12419 |
0 |
0 |
T12 |
72101 |
70547 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1152 |
1152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
476919687 |
0 |
0 |
T1 |
128331 |
127230 |
0 |
0 |
T2 |
38254 |
37952 |
0 |
0 |
T3 |
58595 |
57411 |
0 |
0 |
T4 |
27731 |
26958 |
0 |
0 |
T5 |
418093 |
413398 |
0 |
0 |
T6 |
347169 |
347156 |
0 |
0 |
T9 |
13275 |
12990 |
0 |
0 |
T10 |
18025 |
17832 |
0 |
0 |
T11 |
12680 |
12419 |
0 |
0 |
T12 |
72101 |
70547 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
476919687 |
0 |
0 |
T1 |
128331 |
127230 |
0 |
0 |
T2 |
38254 |
37952 |
0 |
0 |
T3 |
58595 |
57411 |
0 |
0 |
T4 |
27731 |
26958 |
0 |
0 |
T5 |
418093 |
413398 |
0 |
0 |
T6 |
347169 |
347156 |
0 |
0 |
T9 |
13275 |
12990 |
0 |
0 |
T10 |
18025 |
17832 |
0 |
0 |
T11 |
12680 |
12419 |
0 |
0 |
T12 |
72101 |
70547 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
432917426 |
0 |
0 |
T1 |
128331 |
89885 |
0 |
0 |
T2 |
38254 |
29558 |
0 |
0 |
T3 |
58595 |
11194 |
0 |
0 |
T4 |
27731 |
7876 |
0 |
0 |
T5 |
418093 |
236683 |
0 |
0 |
T6 |
347169 |
339148 |
0 |
0 |
T9 |
13275 |
7385 |
0 |
0 |
T10 |
18025 |
11712 |
0 |
0 |
T11 |
12680 |
9328 |
0 |
0 |
T12 |
72101 |
22976 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
44002261 |
0 |
0 |
T1 |
128331 |
37345 |
0 |
0 |
T2 |
38254 |
8394 |
0 |
0 |
T3 |
58595 |
46217 |
0 |
0 |
T4 |
27731 |
19082 |
0 |
0 |
T5 |
418093 |
176715 |
0 |
0 |
T6 |
347169 |
80078 |
0 |
0 |
T9 |
13275 |
5605 |
0 |
0 |
T10 |
18025 |
6120 |
0 |
0 |
T11 |
12680 |
3091 |
0 |
0 |
T12 |
72101 |
47571 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
1152 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
476919687 |
0 |
0 |
T1 |
128331 |
127230 |
0 |
0 |
T2 |
38254 |
37952 |
0 |
0 |
T3 |
58595 |
57411 |
0 |
0 |
T4 |
27731 |
26958 |
0 |
0 |
T5 |
418093 |
413398 |
0 |
0 |
T6 |
347169 |
347156 |
0 |
0 |
T9 |
13275 |
12990 |
0 |
0 |
T10 |
18025 |
17832 |
0 |
0 |
T11 |
12680 |
12419 |
0 |
0 |
T12 |
72101 |
70547 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
477811149 |
0 |
0 |
0 |