Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28054821

1

T1

2521

T2

1093

T3

1427

full_word

9002927

1

T1

1839

T2

845

T3

476

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37057458	1			T1	4360		T2	1938		T3	1903
auto[TlIntgErrCmd]	96	1			T262	2		T263	4		T264	7
auto[TlIntgErrData]	84	1			T262	3		T263	5		T264	8
auto[TlIntgErrBoth]	110	1			T262	5		T263	1		T264	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10303760

1

T1

3875

T2

1729

T3

1778

auto[1]

26753988

1

T1

485

T2

209

T3

125

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6533672	1			T1	2227		T2	991		T3	1369
auto[TlIntgErrNone]	partial	auto[1]	21520884	1			T1	294		T2	102		T3	58
auto[TlIntgErrNone]	full_word	auto[0]	3769963	1			T1	1648		T2	738		T3	409
auto[TlIntgErrNone]	full_word	auto[1]	5232939	1			T1	191		T2	107		T3	67
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T262	1		T263	3		T264	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T262	1		T263	1		T264	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T358	1		T359	1		T360	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T355	1		T361	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T262	1		T263	2		T264	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T262	2		T263	3		T264	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T264	1		T355	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T267	1		T360	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T262	3		T264	1		T352	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T262	2		T263	1		T264	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T352	1		T354	1		T362	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T354	2		T271	1		T358	1