Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.25	94.16	96.15	97.34		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	516558177	9144173	0	0
check_regwen_rd_A	516558177	4140	0	0
check_timeout_rd_A	516558177	3242	0	0
check_trigger_regwen_rd_A	516558177	4180	0	0
consistency_check_period_rd_A	516558177	4450	0	0
creator_sw_cfg_read_lock_rd_A	516558177	3038	0	0
direct_access_address_rd_A	516558177	1993	0	0
direct_access_wdata_0_rd_A	516558177	1361	0	0
direct_access_wdata_1_rd_A	516558177	1600	0	0
integrity_check_period_rd_A	516558177	4254	0	0
intr_enable_rd_A	516558177	5257	0	0
owner_sw_cfg_read_lock_rd_A	516558177	3078	0	0
rot_creator_auth_codesign_read_lock_rd_A	516558177	3203	0	0
rot_creator_auth_state_read_lock_rd_A	516558177	3102	0	0
vendor_test_read_lock_rd_A	516558177	3180	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	9144173	0	0
T6	951669	17695	0	0
T7	273292	64375	0	0
T13	0	123333	0	0
T15	0	60187	0	0
T16	0	169208	0	0
T22	9161	0	0	0
T25	0	80896	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T138	0	73073	0	0
T139	0	110409	0	0
T154	49044	0	0	0
T225	0	43548	0	0
T273	0	35946	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	4140	0	0
T6	951669	9	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	116	0	0
T154	49044	0	0	0
T234	0	74	0	0
T238	0	103	0	0
T252	0	116	0	0
T334	0	14	0	0
T335	0	74	0	0
T336	0	25	0	0
T337	0	150	0	0
T338	0	99	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3242	0	0
T6	951669	9	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	61	0	0
T154	49044	0	0	0
T234	0	65	0	0
T238	0	184	0	0
T252	0	113	0	0
T334	0	30	0	0
T335	0	78	0	0
T336	0	29	0	0
T337	0	110	0	0
T338	0	166	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	4180	0	0
T6	951669	11	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	85	0	0
T154	49044	0	0	0
T234	0	64	0	0
T238	0	96	0	0
T252	0	125	0	0
T334	0	16	0	0
T335	0	87	0	0
T336	0	14	0	0
T337	0	120	0	0
T338	0	86	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	4450	0	0
T6	951669	25	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	154	0	0
T154	49044	0	0	0
T234	0	71	0	0
T238	0	136	0	0
T252	0	107	0	0
T334	0	35	0	0
T335	0	65	0	0
T336	0	56	0	0
T337	0	100	0	0
T338	0	93	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3038	0	0
T6	951669	11	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	90	0	0
T154	49044	0	0	0
T234	0	42	0	0
T238	0	215	0	0
T252	0	81	0	0
T334	0	10	0	0
T335	0	75	0	0
T336	0	30	0	0
T337	0	119	0	0
T338	0	173	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	1993	0	0
T6	951669	19	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	120	0	0
T154	49044	0	0	0
T234	0	53	0	0
T238	0	115	0	0
T252	0	123	0	0
T334	0	16	0	0
T335	0	72	0	0
T336	0	26	0	0
T337	0	158	0	0
T338	0	128	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	1361	0	0
T16	834044	0	0	0
T50	11682	0	0	0
T139	655201	93	0	0
T145	32217	0	0	0
T170	7572	0	0	0
T172	71959	0	0	0
T224	67283	0	0	0
T234	0	12	0	0
T238	0	102	0	0
T252	0	58	0	0
T287	24359	0	0	0
T288	69374	0	0	0
T334	0	1	0	0
T335	0	46	0	0
T336	0	13	0	0
T337	0	99	0	0
T338	0	60	0	0
T339	0	186	0	0
T340	65723	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	1600	0	0
T6	951669	4	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	93	0	0
T154	49044	0	0	0
T234	0	27	0	0
T238	0	116	0	0
T252	0	137	0	0
T334	0	7	0	0
T335	0	89	0	0
T336	0	20	0	0
T337	0	109	0	0
T338	0	109	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	4254	0	0
T6	951669	29	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	105	0	0
T154	49044	0	0	0
T234	0	40	0	0
T238	0	121	0	0
T252	0	164	0	0
T334	0	48	0	0
T335	0	69	0	0
T336	0	13	0	0
T337	0	78	0	0
T338	0	85	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	5257	0	0
T6	951669	37	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T123	0	84	0	0
T133	119824	0	0	0
T139	0	171	0	0
T154	49044	0	0	0
T209	0	8	0	0
T234	0	68	0	0
T238	0	128	0	0
T252	0	153	0	0
T312	0	17	0	0
T334	0	62	0	0
T341	0	44	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3078	0	0
T6	951669	17	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	139	0	0
T154	49044	0	0	0
T234	0	87	0	0
T238	0	147	0	0
T252	0	80	0	0
T334	0	32	0	0
T335	0	106	0	0
T336	0	43	0	0
T337	0	123	0	0
T338	0	150	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3203	0	0
T6	951669	28	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	135	0	0
T154	49044	0	0	0
T234	0	50	0	0
T238	0	113	0	0
T252	0	148	0	0
T334	0	11	0	0
T335	0	99	0	0
T336	0	50	0	0
T337	0	117	0	0
T338	0	147	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3102	0	0
T6	951669	19	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	94	0	0
T154	49044	0	0	0
T234	0	94	0	0
T238	0	111	0	0
T252	0	104	0	0
T334	0	43	0	0
T335	0	96	0	0
T336	0	28	0	0
T337	0	115	0	0
T338	0	123	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516558177	3180	0	0
T6	951669	13	0	0
T7	273292	0	0	0
T22	9161	0	0	0
T34	75450	0	0	0
T68	59761	0	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T109	148310	0	0	0
T133	119824	0	0	0
T139	0	79	0	0
T154	49044	0	0	0
T234	0	58	0	0
T238	0	122	0	0
T252	0	136	0	0
T334	0	23	0	0
T335	0	58	0	0
T336	0	40	0	0
T337	0	110	0	0
T338	0	164	0	0