Unified Coverage Report :: Module Instance :: tb.dut.u_edn_arb

Module Instance : tb.dut.u_edn_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.74	92.31	65.31			100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.74	92.31	65.31			100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.25	94.16	96.15	97.34		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
TOTAL		26	24	92.31
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
112	2	2
118	2	2
122	0	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_arb

	Total	Covered	Percent
Conditions	49	32	65.31
Logical	49	32	65.31
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	1	Not Covered
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	513627880	512743854	0	0
CheckNGreaterZero_A	1157	1157	0	0
GntImpliesReady_A	513627880	300754	0	0
GntImpliesValid_A	513627880	300754	0	0
GrantKnown_A	513627880	512743854	0	0
IdxKnown_A	513627880	512743854	0	0
IndexIsCorrect_A	513627880	300754	0	0
LockArbDecision_A	513627880	22298438	0	0
NoReadyValidNoGrant_A	513627880	490127013	0	0
ReadyAndValidImplyGrant_A	513627880	300754	0	0
ReqAndReadyImplyGrant_A	513627880	300754	0	0
ReqImpliesValid_A	513627880	22616841	0	0
ReqStaysHighUntilGranted0_M	513627880	22298438	0	0
RoundRobin_A	513627880	0	0	1157
ValidKnown_A	513627880	512743854	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	300754	0	0
T1	63673	38	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	3814	0	0
T5	40261	135	0	0
T6	0	2549	0	0
T7	0	273	0	0
T8	16520	45	0	0
T9	58407	475	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	375	0	0
T109	0	125	0	0
T133	0	509	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	300754	0	0
T1	63673	38	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	3814	0	0
T5	40261	135	0	0
T6	0	2549	0	0
T7	0	273	0	0
T8	16520	45	0	0
T9	58407	475	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	375	0	0
T109	0	125	0	0
T133	0	509	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	300754	0	0
T1	63673	38	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	3814	0	0
T5	40261	135	0	0
T6	0	2549	0	0
T7	0	273	0	0
T8	16520	45	0	0
T9	58407	475	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	375	0	0
T109	0	125	0	0
T133	0	509	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	22298438	0	0
T1	63673	2739	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	38163	0	0
T5	40261	7558	0	0
T6	0	98213	0	0
T7	0	20841	0	0
T8	16520	1856	0	0
T9	58407	8524	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	4427	0	0
T109	0	125994	0	0
T133	0	7062	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	490127013	0	0
T1	63673	60497	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	822024	0	0
T5	40261	32216	0	0
T8	16520	14323	0	0
T9	58407	48268	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	300754	0	0
T1	63673	38	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	3814	0	0
T5	40261	135	0	0
T6	0	2549	0	0
T7	0	273	0	0
T8	16520	45	0	0
T9	58407	475	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	375	0	0
T109	0	125	0	0
T133	0	509	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	300754	0	0
T1	63673	38	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	3814	0	0
T5	40261	135	0	0
T6	0	2549	0	0
T7	0	273	0	0
T8	16520	45	0	0
T9	58407	475	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	375	0	0
T109	0	125	0	0
T133	0	509	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	22616841	0	0
T1	63673	2777	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	41985	0	0
T5	40261	7693	0	0
T6	0	100762	0	0
T7	0	21115	0	0
T8	16520	1901	0	0
T9	58407	8999	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	4802	0	0
T109	0	126124	0	0
T133	0	7573	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	22298438	0	0
T1	63673	2739	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	38163	0	0
T5	40261	7558	0	0
T6	0	98213	0	0
T7	0	20841	0	0
T8	16520	1856	0	0
T9	58407	8524	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	4427	0	0
T109	0	125994	0	0
T133	0	7062	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	0	0	1157

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0