Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.25	94.16	96.15	97.34		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.25	94.16	96.15	97.34		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T163,T90

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T68,T73,T99

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T155,T156,T164
1	Covered	T155,T156,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Covered	T70,T71,T171
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T174,T190,T207
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T168,T173,T204
ReadWaitSt->IdleSt	270	Covered	T1,T4,T5
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T155,T156,T164
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T68,T73,T99
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T133,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T155,T156,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T168,T172,T40
MacroEccCorrError->NoError	235	Covered	T68,T73,T99
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T155,T156,T164
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T68,T73,T99

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T40,T163,T90
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T174,T207,T167
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T102,T107,T103
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T68,T73,T99
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T168,T173,T204
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T155,T156,T164
1	0	Covered	T155,T156,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	513627880	512743854	0	0
DigestKnown_A	513627880	512743854	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	513627880	9261	0	0
ErrorKnown_A	513627880	512743854	0	0
FsmStateKnown_A	513627880	512743854	0	0
InitDoneKnown_A	513627880	512743854	0	0
InitReadLocksPartition_A	513627880	124921839	0	0
InitWriteLocksPartition_A	513627880	124921839	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	513627880	512743854	0	0
OtpCmdKnown_A	513627880	512743854	0	0
OtpErrorState_A	513627880	43	0	0
OtpReqKnown_A	513627880	512743854	0	0
OtpSizeKnown_A	513627880	512743854	0	0
OtpWdataKnown_A	513627880	512743854	0	0
ReadLockPropagation_A	513627880	240479929	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	513627880	512743854	0	0
TlulRdataKnown_A	513627880	512743854	0	0
TlulReadOnReadLock_A	513627880	8285	0	0
TlulRerrorKnown_A	513627880	512743854	0	0
TlulRvalidKnown_A	513627880	512743854	0	0
WriteLockPropagation_A	513627880	2661628	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	513627880	30618627	0	0
u_state_regs_A	513627880	512743854	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	9261	0	0
T37	199198	0	0	0
T155	14212	2503	0	0
T156	0	2940	0	0
T164	0	3818	0	0
T176	19098	0	0	0
T177	15628	0	0	0
T178	63957	0	0	0
T179	16559	0	0	0
T180	70524	0	0	0
T181	18550	0	0	0
T182	11812	0	0	0
T183	70577	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	124921839	0	0
T1	63673	593	0	0
T2	13695	5907	0	0
T3	16368	7562	0	0
T4	873470	116720	0	0
T5	40261	608	0	0
T8	16520	1290	0	0
T9	58407	1556	0	0
T10	5360	107	0	0
T11	25770	8731	0	0
T12	47026	38114	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	124921839	0	0
T1	63673	593	0	0
T2	13695	5907	0	0
T3	16368	7562	0	0
T4	873470	116720	0	0
T5	40261	608	0	0
T8	16520	1290	0	0
T9	58407	1556	0	0
T10	5360	107	0	0
T11	25770	8731	0	0
T12	47026	38114	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	43	0	0
T13	660445	0	0	0
T29	14167	0	0	0
T99	29532	0	0	0
T100	36448	0	0	0
T101	37525	0	0	0
T102	66393	0	0	0
T107	50696	0	0	0
T108	84174	0	0	0
T147	8952	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T173	0	1	0	0
T174	11926	1	0	0
T204	0	1	0	0
T207	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	240479929	0	0
T1	63673	26137	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	238457	0	0
T5	40261	9402	0	0
T6	0	354544	0	0
T8	16520	0	0	0
T9	58407	3739	0	0
T10	5360	0	0	0
T11	25770	11232	0	0
T12	47026	0	0	0
T34	0	8229	0	0
T68	0	8576	0	0
T109	0	34134	0	0
T133	0	5926	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	8285	0	0
T1	63673	1	0	0
T2	13695	2	0	0
T3	16368	3	0	0
T4	873470	65	0	0
T5	40261	2	0	0
T6	0	17	0	0
T8	16520	0	0	0
T9	58407	2	0	0
T10	5360	0	0	0
T11	25770	1	0	0
T12	47026	10	0	0
T34	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	2661628	0	0
T4	873470	86395	0	0
T5	40261	0	0	0
T6	951669	0	0	0
T8	16520	0	0	0
T9	58407	4551	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T34	0	8516	0	0
T70	10417	0	0	0
T71	14532	0	0	0
T98	0	6289	0	0
T102	0	462	0	0
T103	0	34178	0	0
T104	0	15235	0	0
T107	0	1330	0	0
T108	0	8505	0	0
T123	0	28468	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	30618627	0	0
T1	63673	42458	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	456555	0	0
T5	40261	25901	0	0
T8	16520	0	0	0
T9	58407	36959	0	0
T10	5360	0	0	0
T11	25770	4169	0	0
T12	47026	0	0	0
T34	0	63978	0	0
T68	0	49684	0	0
T109	0	117145	0	0
T133	0	4183	0	0
T210	0	2875	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T69,T85

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T68,T73,T168

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T155,T156,T164
1	Covered	T155,T156,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T133

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T133

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Covered	T70,T71,T171
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T72,T174,T207
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T4,T8
ReadWaitSt->ErrorSt	276	Covered	T172,T219,T157
ReadWaitSt->IdleSt	270	Covered	T1,T4,T8
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T155,T156,T164
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T22,T68,T73
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T11,T133,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T155,T156,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T22,T69,T85
MacroEccCorrError->NoError	235	Covered	T68,T73,T215
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T155,T156,T164
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T22,T68,T73

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T133
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T22,T69,T85
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T72,T220,T221
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T102,T107,T103
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T68,T73,T168
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T172,T219,T157
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T4,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T4,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T155,T156,T164
1	0	Covered	T155,T156,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	513627880	512743854	0	0
DigestKnown_A	513627880	512743854	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	513627880	18004	0	0
ErrorKnown_A	513627880	512743854	0	0
FsmStateKnown_A	513627880	512743854	0	0
InitDoneKnown_A	513627880	512743854	0	0
InitReadLocksPartition_A	513627880	125106226	0	0
InitWriteLocksPartition_A	513627880	125106226	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	513627880	512743854	0	0
OtpCmdKnown_A	513627880	512743854	0	0
OtpErrorState_A	513627880	28	0	0
OtpReqKnown_A	513627880	512743854	0	0
OtpSizeKnown_A	513627880	512743854	0	0
OtpWdataKnown_A	513627880	512743854	0	0
ReadLockPropagation_A	513627880	245937608	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	513627880	512743854	0	0
TlulRdataKnown_A	513627880	512743854	0	0
TlulReadOnReadLock_A	513627880	8062	0	0
TlulRerrorKnown_A	513627880	512743854	0	0
TlulRvalidKnown_A	513627880	512743854	0	0
WriteLockPropagation_A	513627880	844986	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	513627880	10040905	0	0
u_state_regs_A	513627880	512743854	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	18004	0	0
T37	199198	0	0	0
T155	14212	2503	0	0
T156	0	2940	0	0
T164	0	3818	0	0
T165	0	2658	0	0
T166	0	3569	0	0
T169	0	2516	0	0
T176	19098	0	0	0
T177	15628	0	0	0
T178	63957	0	0	0
T179	16559	0	0	0
T180	70524	0	0	0
T181	18550	0	0	0
T182	11812	0	0	0
T183	70577	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	125106226	0	0
T1	63673	678	0	0
T2	13695	5958	0	0
T3	16368	7613	0	0
T4	873470	118539	0	0
T5	40261	693	0	0
T8	16520	1341	0	0
T9	58407	1794	0	0
T10	5360	124	0	0
T11	25770	8799	0	0
T12	47026	38165	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	125106226	0	0
T1	63673	678	0	0
T2	13695	5958	0	0
T3	16368	7613	0	0
T4	873470	118539	0	0
T5	40261	693	0	0
T8	16520	1341	0	0
T9	58407	1794	0	0
T10	5360	124	0	0
T11	25770	8799	0	0
T12	47026	38165	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	28	0	0
T14	52605	0	0	0
T46	14170	0	0	0
T69	11105	0	0	0
T72	9986	1	0	0
T73	24004	0	0	0
T112	41770	0	0	0
T113	26369	0	0	0
T134	5204	0	0	0
T157	0	1	0	0
T160	11685	0	0	0
T172	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T210	30697	0	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	245937608	0	0
T1	63673	16380	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	237928	0	0
T5	40261	18571	0	0
T6	0	352202	0	0
T8	16520	0	0	0
T9	58407	3017	0	0
T10	5360	0	0	0
T11	25770	14642	0	0
T12	47026	0	0	0
T34	0	11215	0	0
T68	0	7870	0	0
T109	0	52089	0	0
T133	0	5910	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	8062	0	0
T1	63673	4	0	0
T2	13695	2	0	0
T3	16368	0	0	0
T4	873470	68	0	0
T5	40261	4	0	0
T6	0	13	0	0
T8	16520	0	0	0
T9	58407	0	0	0
T10	5360	0	0	0
T11	25770	1	0	0
T12	47026	12	0	0
T34	0	14	0	0
T109	0	8	0	0
T154	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	844986	0	0
T1	63673	15539	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	38501	0	0
T5	40261	0	0	0
T8	16520	0	0	0
T9	58407	0	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T93	0	15642	0	0
T95	0	7039	0	0
T103	0	17148	0	0
T105	0	8714	0	0
T123	0	6556	0	0
T133	0	6132	0	0
T209	0	2917	0	0
T224	0	10528	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	10040905	0	0
T1	63673	42390	0	0
T2	13695	0	0	0
T3	16368	0	0	0
T4	873470	214385	0	0
T5	40261	0	0	0
T8	16520	0	0	0
T9	58407	0	0	0
T10	5360	0	0	0
T11	25770	0	0	0
T12	47026	0	0	0
T72	0	3490	0	0
T103	0	163286	0	0
T105	0	58019	0	0
T123	0	38675	0	0
T133	0	28139	0	0
T209	0	83298	0	0
T210	0	2841	0	0
T211	0	2501	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513627880	512743854	0	0
T1	63673	63274	0	0
T2	13695	13454	0	0
T3	16368	16101	0	0
T4	873470	864009	0	0
T5	40261	39909	0	0
T8	16520	16224	0	0
T9	58407	57267	0	0
T10	5360	5307	0	0
T11	25770	25491	0	0
T12	47026	46766	0	0