Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_lc_gate
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.86 98.04 88.89 85.71 91.67 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_lc_gate 83.66 98.04 88.89 85.71 95.65 50.00



Module Instance : tb.dut.u_tlul_lc_gate

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.66 98.04 88.89 85.71 95.65 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.41 99.21 92.86 85.71 96.77 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.25 94.16 96.15 97.34 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d 100.00 100.00
u_err_en_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_tlul_err_resp 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
TOTAL515098.04
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282796.43
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
==> MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Module : tlul_lc_gate
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0CoveredT6,T7,T13
1CoveredT1,T4,T5

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0CoveredT6,T13,T15
1CoveredT1,T4,T5

FSM Coverage for Module : tlul_lc_gate
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 6 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T4,T5
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T4,T5
StFlush 184 Covered T16,T17,T18
StOutstanding 174 Covered T1,T4,T5


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T1,T4,T5
StError->StErrorOutstanding 203 Covered T1,T4,T5
StErrorOutstanding->StActive 211 Covered T1,T4,T5
StFlush->StActive 196 Covered T16,T17,T18
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Covered T1,T4,T5
StOutstanding->StFlush 184 Covered T16,T17,T18



Branch Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
Branches 24 22 91.67
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 12 85.71
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T1,T4,T5
StActive 0 - - - - - - Covered T1,T4,T5
StActive - 1 - - - - - Covered T1,T4,T5
StActive - 0 - - - - - Covered T1,T4,T5
StOutstanding - - 1 - - - - Covered T1,T4,T5
StOutstanding - - 0 - - - - Covered T6,T7,T13
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T16,T17,T18
StFlush - - - 0 0 - - Not Covered
StError - - - - - 1 - Covered T1,T4,T5
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T4,T5
StErrorOutstanding - - - - - - 0 Covered T6,T13,T15
default - - - - - - - Covered T19,T20,T21


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_lc_gate
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 513627880 0 0 0
u_state_regs_A 513627880 512743854 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513627880 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513627880 512743854 0 0
T1 63673 63274 0 0
T2 13695 13454 0 0
T3 16368 16101 0 0
T4 873470 864009 0 0
T5 40261 39909 0 0
T8 16520 16224 0 0
T9 58407 57267 0 0
T10 5360 5307 0 0
T11 25770 25491 0 0
T12 47026 46766 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate
Line No.TotalCoveredPercent
TOTAL515098.04
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282796.43
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 1 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
==> MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_lc_gate
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0CoveredT6,T7,T13
1CoveredT1,T4,T5

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0CoveredT6,T13,T15
1CoveredT1,T4,T5

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 6 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T4,T5
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T4,T5
StFlush 184 Covered T16,T17,T18
StOutstanding 174 Covered T1,T4,T5


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T1,T4,T5
StError->StErrorOutstanding 203 Covered T1,T4,T5
StErrorOutstanding->StActive 211 Covered T1,T4,T5
StFlush->StActive 196 Covered T16,T17,T18
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Covered T1,T4,T5
StOutstanding->StFlush 184 Covered T16,T17,T18



Branch Coverage for Instance : tb.dut.u_tlul_lc_gate
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 13 12 92.31
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
StActive 1 - - - - - - Covered T1,T4,T5
StActive 0 - - - - - - Covered T1,T4,T5
StActive - 1 - - - - - Covered T1,T4,T5
StActive - 0 - - - - - Covered T1,T4,T5
StOutstanding - - 1 - - - - Covered T1,T4,T5
StOutstanding - - 0 - - - - Covered T6,T7,T13
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T16,T17,T18
StFlush - - - 0 0 - - Excluded VC_COV_UNR
StError - - - - - 1 - Covered T1,T4,T5
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T4,T5
StErrorOutstanding - - - - - - 0 Covered T6,T13,T15
default - - - - - - - Covered T19,T20,T21


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 513627880 0 0 0
u_state_regs_A 513627880 512743854 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513627880 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513627880 512743854 0 0
T1 63673 63274 0 0
T2 13695 13454 0 0
T3 16368 16101 0 0
T4 873470 864009 0 0
T5 40261 39909 0 0
T8 16520 16224 0 0
T9 58407 57267 0 0
T10 5360 5307 0 0
T11 25770 25491 0 0
T12 47026 46766 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%