Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6708102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6639071

1

T1

627

T2

107

T3

178

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7764435	1			T1	2084		T2	453		T3	300
values[0x0]	2133245	1			T1	117		T2	65		T3	108
values[0x1]	3449493	1			T1	94		T2	81		T3	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4359582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8987591

1

T1

1062

T2

237

T3

254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51039	1			T1	7		T9	2		T4	14
valid_sources[0x01]	48155	1			T1	9		T3	3		T9	3
valid_sources[0x02]	44280	1			T1	5		T3	1		T9	6
valid_sources[0x03]	45194	1			T1	7		T3	3		T11	1
valid_sources[0x04]	44953	1			T1	5		T3	4		T9	2
valid_sources[0x05]	48467	1			T1	9		T3	2		T9	2
valid_sources[0x06]	57588	1			T1	12		T3	2		T9	14
valid_sources[0x07]	57826	1			T1	14		T9	7		T4	14
valid_sources[0x08]	67221	1			T1	33		T3	1		T9	12
valid_sources[0x09]	52644	1			T1	18		T3	2		T9	4
valid_sources[0x0a]	50257	1			T1	20		T3	3		T11	1
valid_sources[0x0b]	49489	1			T1	29		T3	1		T9	6
valid_sources[0x0c]	100374	1			T1	13		T9	6		T4	11
valid_sources[0x0d]	50928	1			T1	12		T10	2		T9	5
valid_sources[0x0e]	51011	1			T1	1		T3	3		T9	5
valid_sources[0x0f]	58006	1			T1	7		T3	1		T9	4
valid_sources[0x10]	46133	1			T1	10		T3	1		T11	5
valid_sources[0x11]	49920	1			T1	8		T3	2		T9	1
valid_sources[0x12]	45999	1			T1	13		T3	1		T9	8
valid_sources[0x13]	47206	1			T1	7		T3	2		T9	12
valid_sources[0x14]	61151	1			T1	13		T3	3		T9	7
valid_sources[0x15]	46086	1			T1	4		T3	3		T9	5
valid_sources[0x16]	59866	1			T1	10		T9	8		T4	11
valid_sources[0x17]	48654	1			T1	6		T3	4		T9	4
valid_sources[0x18]	137992	1			T1	7		T3	2		T9	3
valid_sources[0x19]	45949	1			T1	3		T3	4		T9	9
valid_sources[0x1a]	53074	1			T1	4		T3	4		T9	9
valid_sources[0x1b]	45493	1			T1	19		T3	1		T9	3
valid_sources[0x1c]	48303	1			T1	2		T3	1		T9	7
valid_sources[0x1d]	54040	1			T3	3		T9	7		T4	15
valid_sources[0x1e]	51162	1			T1	3		T3	2		T9	5
valid_sources[0x1f]	51075	1			T1	28		T3	7		T10	2
valid_sources[0x20]	53007	1			T1	9		T3	1		T9	5
valid_sources[0x21]	49685	1			T1	13		T3	4		T9	4
valid_sources[0x22]	45873	1			T1	1		T3	4		T9	2
valid_sources[0x23]	52019	1			T1	4		T3	2		T9	6
valid_sources[0x24]	47067	1			T1	16		T3	5		T9	5
valid_sources[0x25]	49051	1			T3	2		T9	4		T4	8
valid_sources[0x26]	47393	1			T1	3		T3	3		T9	15
valid_sources[0x27]	46034	1			T1	10		T11	1		T9	5
valid_sources[0x28]	47030	1			T1	17		T3	2		T10	3
valid_sources[0x29]	45443	1			T1	12		T3	2		T11	1
valid_sources[0x2a]	46872	1			T1	2		T3	3		T9	2
valid_sources[0x2b]	47275	1			T1	31		T3	2		T10	2
valid_sources[0x2c]	47768	1			T1	1		T9	10		T4	9
valid_sources[0x2d]	46224	1			T1	14		T3	3		T11	1
valid_sources[0x2e]	47374	1			T1	6		T3	1		T9	4
valid_sources[0x2f]	46493	1			T1	11		T3	4		T9	5
valid_sources[0x30]	47815	1			T1	3		T10	5		T9	4
valid_sources[0x31]	51279	1			T1	7		T3	2		T9	4
valid_sources[0x32]	53808	1			T1	9		T2	46		T3	3
valid_sources[0x33]	48510	1			T1	14		T3	1		T9	6
valid_sources[0x34]	49313	1			T1	10		T3	1		T11	2
valid_sources[0x35]	59621	1			T1	10		T3	3		T9	6
valid_sources[0x36]	49884	1			T2	400		T9	6		T4	13
valid_sources[0x37]	60674	1			T1	1		T3	2		T9	6
valid_sources[0x38]	45663	1			T1	13		T9	4		T4	13
valid_sources[0x39]	50482	1			T1	12		T9	7		T4	8
valid_sources[0x3a]	49274	1			T1	21		T3	3		T9	4
valid_sources[0x3b]	60927	1			T1	19		T3	1		T9	2
valid_sources[0x3c]	47261	1			T1	13		T3	2		T11	1
valid_sources[0x3d]	45233	1			T1	4		T3	3		T9	8
valid_sources[0x3e]	73307	1			T1	2		T3	5		T9	10
valid_sources[0x3f]	48467	1			T1	11		T10	4		T9	5
valid_sources[0x40]	46987	1			T1	7		T9	5		T4	5
valid_sources[0x41]	49565	1			T1	8		T3	3		T9	5
valid_sources[0x42]	49341	1			T1	26		T3	1		T9	6
valid_sources[0x43]	47180	1			T1	7		T3	5		T9	9
valid_sources[0x44]	59701	1			T1	4		T3	4		T9	3
valid_sources[0x45]	53102	1			T1	11		T3	1		T9	5
valid_sources[0x46]	50358	1			T1	2		T3	5		T11	4
valid_sources[0x47]	46716	1			T1	5		T3	2		T9	3
valid_sources[0x48]	57436	1			T1	9		T3	4		T9	4
valid_sources[0x49]	47548	1			T1	7		T3	6		T9	4
valid_sources[0x4a]	52549	1			T1	11		T3	1		T9	6
valid_sources[0x4b]	44698	1			T1	4		T3	1		T9	1
valid_sources[0x4c]	45998	1			T1	8		T3	4		T9	1
valid_sources[0x4d]	46226	1			T1	4		T3	2		T9	6
valid_sources[0x4e]	47116	1			T1	12		T9	3		T4	24
valid_sources[0x4f]	45840	1			T1	5		T2	140		T9	2
valid_sources[0x50]	56375	1			T1	10		T3	4		T10	1
valid_sources[0x51]	47844	1			T1	7		T11	2		T9	6
valid_sources[0x52]	47345	1			T1	11		T3	1		T9	1
valid_sources[0x53]	48622	1			T1	4		T3	1		T10	5
valid_sources[0x54]	50039	1			T1	14		T3	1		T10	3
valid_sources[0x55]	50754	1			T1	2		T3	2		T9	6
valid_sources[0x56]	53972	1			T3	4		T9	4		T4	9
valid_sources[0x57]	46455	1			T1	2		T3	1		T9	4
valid_sources[0x58]	47851	1			T1	3		T3	2		T9	8
valid_sources[0x59]	50034	1			T1	4		T3	2		T11	1
valid_sources[0x5a]	56371	1			T1	15		T9	5		T4	6
valid_sources[0x5b]	49286	1			T1	10		T11	1		T9	3
valid_sources[0x5c]	45286	1			T1	4		T3	2		T9	5
valid_sources[0x5d]	47583	1			T1	1		T3	3		T9	5
valid_sources[0x5e]	47337	1			T1	15		T9	6		T4	5
valid_sources[0x5f]	106581	1			T1	20		T3	2		T9	3
valid_sources[0x60]	49669	1			T1	18		T9	5		T4	12
valid_sources[0x61]	46555	1			T1	5		T3	2		T10	1
valid_sources[0x62]	46623	1			T9	2		T4	11		T13	6
valid_sources[0x63]	47429	1			T1	5		T3	3		T9	10
valid_sources[0x64]	45915	1			T1	11		T3	1		T10	3
valid_sources[0x65]	47279	1			T1	4		T3	2		T9	4
valid_sources[0x66]	49004	1			T1	9		T9	3		T4	4
valid_sources[0x67]	63056	1			T1	6		T10	1		T9	10
valid_sources[0x68]	46664	1			T1	19		T3	2		T9	3
valid_sources[0x69]	60351	1			T1	9		T3	2		T9	3
valid_sources[0x6a]	57765	1			T1	10		T3	1		T9	5
valid_sources[0x6b]	47598	1			T1	16		T3	2		T11	1
valid_sources[0x6c]	46499	1			T1	6		T9	10		T4	13
valid_sources[0x6d]	49558	1			T1	4		T3	2		T9	6
valid_sources[0x6e]	65075	1			T1	5		T3	5		T10	1
valid_sources[0x6f]	57004	1			T1	4		T3	2		T9	11
valid_sources[0x70]	49483	1			T1	13		T3	5		T9	6
valid_sources[0x71]	53882	1			T1	9		T3	4		T9	3
valid_sources[0x72]	45261	1			T1	10		T9	7		T4	9
valid_sources[0x73]	45539	1			T1	12		T3	2		T9	4
valid_sources[0x74]	47268	1			T1	20		T9	5		T4	6
valid_sources[0x75]	46183	1			T1	20		T3	3		T9	5
valid_sources[0x76]	59908	1			T1	7		T3	3		T10	5
valid_sources[0x77]	45308	1			T1	8		T9	2		T4	5
valid_sources[0x78]	56063	1			T1	8		T3	1		T9	6
valid_sources[0x79]	51334	1			T1	5		T3	3		T9	6
valid_sources[0x7a]	60338	1			T1	3		T9	4		T4	14
valid_sources[0x7b]	48166	1			T1	6		T3	1		T9	9
valid_sources[0x7c]	48551	1			T1	9		T9	6		T4	10
valid_sources[0x7d]	47099	1			T1	5		T11	1		T9	8
valid_sources[0x7e]	48477	1			T1	16		T3	3		T11	1
valid_sources[0x7f]	53262	1			T1	13		T3	1		T9	4
valid_sources[0x80]	47007	1			T1	3		T3	2		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3188342

1

T1

535

T2

52

T3

89

values[0x0]

all_enables

biggest_size

1762386

1

T1

64

T2

26

T3

50

values[0x1]

all_enables

biggest_size

1688343

1

T1

28

T2

29

T3

39

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	229870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8251457

1

T1

60

T4

40

T5

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2111154	1			T1	30		T4	20		T5	10
values[0x0]	3091891	1			T1	15		T4	9		T5	5
values[0x1]	3278282	1			T1	15		T4	11		T5	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	83382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8397945

1

T1

60

T4

40

T5

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32912	1			T18	4		T7	233		T107	1
valid_sources[0x01]	33242	1			T7	249		T117	1		T15	228
valid_sources[0x02]	32593	1			T19	3		T114	3		T7	257
valid_sources[0x03]	33473	1			T114	1		T7	280		T15	199
valid_sources[0x04]	32203	1			T7	266		T116	1		T15	258
valid_sources[0x05]	35075	1			T19	3		T7	255		T107	1
valid_sources[0x06]	33522	1			T7	274		T15	211		T16	15
valid_sources[0x07]	32793	1			T5	2		T19	1		T48	2
valid_sources[0x08]	33818	1			T45	2		T73	1		T7	312
valid_sources[0x09]	32431	1			T18	8		T7	262		T107	1
valid_sources[0x0a]	33441	1			T19	2		T73	1		T7	256
valid_sources[0x0b]	33315	1			T5	1		T18	1		T19	1
valid_sources[0x0c]	31603	1			T4	7		T5	2		T7	282
valid_sources[0x0d]	34011	1			T7	313		T116	1		T55	1
valid_sources[0x0e]	33000	1			T18	1		T114	2		T7	250
valid_sources[0x0f]	34004	1			T18	3		T114	1		T7	243
valid_sources[0x10]	32844	1			T114	1		T7	280		T107	1
valid_sources[0x11]	33497	1			T19	2		T114	1		T7	259
valid_sources[0x12]	31377	1			T114	1		T7	244		T55	2
valid_sources[0x13]	34228	1			T48	1		T114	1		T7	321
valid_sources[0x14]	32787	1			T5	2		T18	1		T19	2
valid_sources[0x15]	32379	1			T1	60		T18	5		T19	1
valid_sources[0x16]	31241	1			T7	229		T15	240		T16	42
valid_sources[0x17]	33397	1			T6	1		T7	251		T15	221
valid_sources[0x18]	34273	1			T18	2		T48	2		T7	257
valid_sources[0x19]	31820	1			T6	1		T114	1		T7	281
valid_sources[0x1a]	34068	1			T7	255		T55	2		T15	216
valid_sources[0x1b]	33210	1			T5	1		T7	227		T55	3
valid_sources[0x1c]	35143	1			T114	1		T7	265		T15	218
valid_sources[0x1d]	33546	1			T48	2		T7	259		T55	2
valid_sources[0x1e]	33157	1			T73	1		T114	2		T7	239
valid_sources[0x1f]	32538	1			T18	3		T7	248		T110	1
valid_sources[0x20]	32441	1			T6	1		T7	263		T15	236
valid_sources[0x21]	31631	1			T18	2		T114	1		T7	244
valid_sources[0x22]	32726	1			T19	1		T114	2		T7	264
valid_sources[0x23]	33529	1			T18	1		T45	1		T114	1
valid_sources[0x24]	34668	1			T48	1		T7	251		T116	1
valid_sources[0x25]	33520	1			T114	1		T7	264		T117	1
valid_sources[0x26]	32493	1			T18	3		T6	1		T73	1
valid_sources[0x27]	33821	1			T48	1		T7	278		T115	2
valid_sources[0x28]	33884	1			T18	3		T19	1		T7	275
valid_sources[0x29]	34077	1			T19	3		T6	1		T114	1
valid_sources[0x2a]	35319	1			T48	1		T114	2		T7	259
valid_sources[0x2b]	33294	1			T19	1		T7	240		T110	1
valid_sources[0x2c]	32816	1			T114	1		T7	258		T117	1
valid_sources[0x2d]	33540	1			T4	1		T7	279		T110	2
valid_sources[0x2e]	33246	1			T7	247		T55	1		T107	1
valid_sources[0x2f]	33956	1			T7	262		T15	252		T16	53
valid_sources[0x30]	33758	1			T114	1		T7	264		T116	1
valid_sources[0x31]	32730	1			T114	6		T7	250		T55	1
valid_sources[0x32]	31970	1			T4	2		T45	2		T7	228
valid_sources[0x33]	33109	1			T7	295		T110	1		T15	231
valid_sources[0x34]	34455	1			T18	1		T7	216		T15	204
valid_sources[0x35]	34576	1			T18	2		T7	255		T116	1
valid_sources[0x36]	33099	1			T114	1		T7	256		T55	1
valid_sources[0x37]	30905	1			T45	1		T48	1		T114	1
valid_sources[0x38]	32171	1			T7	234		T15	234		T16	13
valid_sources[0x39]	32190	1			T7	274		T15	214		T16	12
valid_sources[0x3a]	33059	1			T7	264		T110	1		T15	219
valid_sources[0x3b]	34429	1			T48	2		T7	254		T55	1
valid_sources[0x3c]	33245	1			T18	1		T19	2		T73	3
valid_sources[0x3d]	34662	1			T18	4		T19	1		T7	265
valid_sources[0x3e]	34865	1			T114	1		T7	249		T55	1
valid_sources[0x3f]	32700	1			T48	1		T7	267		T110	1
valid_sources[0x40]	34335	1			T114	3		T7	223		T15	221
valid_sources[0x41]	32985	1			T114	1		T7	253		T15	206
valid_sources[0x42]	32360	1			T18	2		T19	1		T7	263
valid_sources[0x43]	34478	1			T18	2		T7	249		T117	1
valid_sources[0x44]	32387	1			T19	1		T48	1		T7	247
valid_sources[0x45]	32035	1			T7	288		T110	1		T15	228
valid_sources[0x46]	33079	1			T19	1		T7	255		T107	1
valid_sources[0x47]	31645	1			T18	5		T48	1		T7	238
valid_sources[0x48]	31532	1			T19	1		T6	1		T48	1
valid_sources[0x49]	32325	1			T18	4		T7	259		T107	1
valid_sources[0x4a]	33310	1			T6	1		T48	1		T7	270
valid_sources[0x4b]	34314	1			T18	1		T114	1		T7	268
valid_sources[0x4c]	34130	1			T45	1		T7	213		T15	256
valid_sources[0x4d]	32875	1			T18	2		T7	235		T110	2
valid_sources[0x4e]	32662	1			T48	1		T7	270		T106	2
valid_sources[0x4f]	34840	1			T48	2		T7	236		T15	205
valid_sources[0x50]	31974	1			T114	1		T7	253		T15	228
valid_sources[0x51]	34252	1			T18	1		T45	1		T48	1
valid_sources[0x52]	32674	1			T4	4		T18	1		T19	1
valid_sources[0x53]	33192	1			T45	4		T7	275		T55	1
valid_sources[0x54]	33798	1			T18	3		T19	1		T114	1
valid_sources[0x55]	32482	1			T19	1		T6	2		T7	260
valid_sources[0x56]	32343	1			T7	224		T15	249		T16	19
valid_sources[0x57]	32618	1			T7	244		T110	1		T15	225
valid_sources[0x58]	32423	1			T18	2		T7	283		T107	1
valid_sources[0x59]	31727	1			T19	1		T114	1		T7	238
valid_sources[0x5a]	33864	1			T18	5		T114	2		T7	275
valid_sources[0x5b]	32942	1			T114	1		T7	245		T110	1
valid_sources[0x5c]	32271	1			T73	1		T7	298		T55	2
valid_sources[0x5d]	35343	1			T18	5		T19	1		T114	3
valid_sources[0x5e]	34466	1			T7	273		T55	1		T15	211
valid_sources[0x5f]	31241	1			T114	2		T7	266		T15	235
valid_sources[0x60]	32746	1			T7	248		T117	5		T55	1
valid_sources[0x61]	32242	1			T73	1		T7	299		T15	227
valid_sources[0x62]	34388	1			T4	4		T19	3		T48	1
valid_sources[0x63]	34247	1			T114	1		T7	256		T117	2
valid_sources[0x64]	33039	1			T7	270		T107	1		T15	201
valid_sources[0x65]	34109	1			T18	5		T114	1		T7	266
valid_sources[0x66]	32764	1			T19	1		T7	273		T106	8
valid_sources[0x67]	32231	1			T7	278		T117	1		T15	221
valid_sources[0x68]	32522	1			T114	3		T7	247		T116	1
valid_sources[0x69]	31948	1			T4	9		T19	1		T7	242
valid_sources[0x6a]	33906	1			T19	1		T7	238		T55	1
valid_sources[0x6b]	32443	1			T18	4		T7	257		T110	2
valid_sources[0x6c]	33926	1			T19	1		T114	3		T7	263
valid_sources[0x6d]	31492	1			T18	3		T7	258		T15	204
valid_sources[0x6e]	33942	1			T48	1		T114	4		T7	286
valid_sources[0x6f]	33082	1			T5	1		T18	1		T7	279
valid_sources[0x70]	33070	1			T114	1		T7	282		T15	216
valid_sources[0x71]	34640	1			T48	1		T114	2		T7	288
valid_sources[0x72]	34618	1			T6	1		T7	254		T110	1
valid_sources[0x73]	33665	1			T7	268		T15	242		T16	30
valid_sources[0x74]	32687	1			T18	2		T19	1		T48	1
valid_sources[0x75]	35950	1			T18	3		T7	263		T110	2
valid_sources[0x76]	32791	1			T114	1		T7	258		T15	223
valid_sources[0x77]	33078	1			T19	1		T48	3		T7	247
valid_sources[0x78]	33492	1			T7	257		T15	218		T16	30
valid_sources[0x79]	34253	1			T7	218		T115	17		T117	2
valid_sources[0x7a]	32737	1			T19	1		T7	287		T15	259
valid_sources[0x7b]	34197	1			T7	240		T15	206		T16	22
valid_sources[0x7c]	31175	1			T7	268		T110	1		T15	229
valid_sources[0x7d]	32138	1			T18	2		T19	2		T48	1
valid_sources[0x7e]	31578	1			T114	2		T7	222		T110	2
valid_sources[0x7f]	33224	1			T114	1		T7	241		T55	1
valid_sources[0x80]	33317	1			T18	5		T73	1		T114	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2097056

1

T1

30

T4

20

T5

10

values[0x0]

all_enables

biggest_size

3076397

1

T1

15

T4

9

T5

5

values[0x1]

all_enables

biggest_size

3078004

1

T1

15

T4

11

T5

5