SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19354714 | 1 | T1 | 2281 | T2 | 586 | T3 | 487 | ||||
auto[1] | 11430857 | 1 | T1 | 14 | T2 | 13 | T3 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30785358 | 1 | T1 | 2295 | T2 | 599 | T3 | 505 | ||||
values[1] | 22 | 1 | T292 | 1 | T293 | 2 | T294 | 2 | ||||
values[2] | 7 | 1 | T294 | 1 | T406 | 1 | T409 | 4 | ||||
values[3] | 107 | 1 | T292 | 4 | T293 | 3 | T294 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30785366 | 1 | T1 | 2295 | T2 | 599 | T3 | 505 | ||||
values[1] | 13 | 1 | T292 | 1 | T293 | 4 | T405 | 1 | ||||
values[2] | 6 | 1 | T405 | 2 | T301 | 1 | T413 | 1 | ||||
values[3] | 99 | 1 | T292 | 3 | T293 | 5 | T294 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 30785251 | 1 | T1 | 2295 | T2 | 599 | T3 | 505 | ||||
auto[TlIntgErrCmd] | 115 | 1 | T292 | 3 | T293 | 6 | T294 | 6 | ||||
auto[TlIntgErrData] | 107 | 1 | T292 | 5 | T293 | 11 | T294 | 6 | ||||
auto[TlIntgErrBoth] | 98 | 1 | T292 | 2 | T293 | 3 | T294 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3698487 | 0 | T1 | 28 | T19 | 58 | T7 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3698269 | 1 | T1 | 28 | T19 | 58 | T7 | 40 | ||||
values[1] | 19 | 1 | T293 | 1 | T294 | 2 | T405 | 1 | ||||
values[2] | 10 | 1 | T293 | 1 | T408 | 2 | T407 | 1 | ||||
values[3] | 110 | 1 | T292 | 5 | T293 | 8 | T294 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3698263 | 1 | T1 | 28 | T19 | 58 | T7 | 40 | ||||
values[1] | 26 | 1 | T293 | 3 | T294 | 4 | T405 | 1 | ||||
values[2] | 5 | 1 | T292 | 1 | T293 | 1 | T405 | 1 | ||||
values[3] | 107 | 1 | T292 | 3 | T293 | 4 | T294 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3698167 | 1 | T1 | 28 | T19 | 58 | T7 | 40 | ||||
auto[TlIntgErrCmd] | 96 | 1 | T292 | 4 | T293 | 7 | T294 | 8 | ||||
auto[TlIntgErrData] | 102 | 1 | T292 | 4 | T293 | 4 | T294 | 3 | ||||
auto[TlIntgErrBoth] | 122 | 1 | T292 | 2 | T293 | 9 | T294 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |