Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23148654

1

T1

1668

T2

492

T3

327

full_word

7636917

1

T1

627

T2

107

T3

178

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30785251	1			T1	2295		T2	599		T3	505
auto[TlIntgErrCmd]	115	1			T292	3		T293	6		T294	6
auto[TlIntgErrData]	107	1			T292	5		T293	11		T294	6
auto[TlIntgErrBoth]	98	1			T292	2		T293	3		T294	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8971967

1

T1

2084

T2

453

T3

300

auto[1]

21813604

1

T1

211

T2

146

T3

205

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5660901	1			T1	1549		T2	401		T3	211
auto[TlIntgErrNone]	partial	auto[1]	17487450	1			T1	119		T2	91		T3	116
auto[TlIntgErrNone]	full_word	auto[0]	3310918	1			T1	535		T2	52		T3	89
auto[TlIntgErrNone]	full_word	auto[1]	4325982	1			T1	92		T2	55		T3	89
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T293	3		T294	3		T405	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T292	2		T293	3		T294	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T292	1		T406	1		T407	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T408	1		T409	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T292	2		T293	7		T294	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T292	2		T293	4		T294	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T294	1		T410	1		T296	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T292	1		T405	1		T406	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T292	1		T293	1		T294	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T292	1		T293	2		T294	7
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T405	1		T411	1		T412	1