SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16332947 | 1 | T1 | 1623 | T2 | 778 | T3 | 780 | ||||
auto[1] | 9484240 | 1 | T1 | 2 | T2 | 1 | T3 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 25816991 | 1 | T1 | 1625 | T2 | 779 | T3 | 802 | ||||
values[1] | 25 | 1 | T249 | 4 | T250 | 1 | T251 | 2 | ||||
values[2] | 1 | 1 | T371 | 1 | - | - | - | - | ||||
values[3] | 100 | 1 | T249 | 9 | T250 | 4 | T251 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 25816999 | 1 | T1 | 1625 | T2 | 779 | T3 | 802 | ||||
values[1] | 23 | 1 | T249 | 1 | T250 | 1 | T251 | 2 | ||||
values[2] | 10 | 1 | T250 | 1 | T372 | 1 | T373 | 1 | ||||
values[3] | 79 | 1 | T249 | 5 | T250 | 3 | T251 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 25816897 | 1 | T1 | 1625 | T2 | 779 | T3 | 802 | ||||
auto[TlIntgErrCmd] | 102 | 1 | T249 | 9 | T250 | 3 | T251 | 5 | ||||
auto[TlIntgErrData] | 94 | 1 | T249 | 3 | T250 | 4 | T251 | 8 | ||||
auto[TlIntgErrBoth] | 94 | 1 | T249 | 8 | T250 | 3 | T251 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 2248002 | 0 | T6 | 36113 | T15 | 96 | T13 | 41905 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2247800 | 1 | T6 | 36113 | T15 | 96 | T13 | 41905 | ||||
values[1] | 22 | 1 | T249 | 3 | T250 | 1 | T251 | 1 | ||||
values[2] | 5 | 1 | T374 | 1 | T255 | 1 | T375 | 1 | ||||
values[3] | 92 | 1 | T249 | 9 | T250 | 4 | T251 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2247817 | 1 | T6 | 36113 | T15 | 96 | T13 | 41905 | ||||
values[1] | 23 | 1 | T251 | 2 | T372 | 1 | T373 | 3 | ||||
values[2] | 5 | 1 | T249 | 1 | T376 | 1 | T377 | 1 | ||||
values[3] | 92 | 1 | T249 | 7 | T250 | 4 | T251 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 2247712 | 1 | T6 | 36113 | T15 | 96 | T13 | 41905 | ||||
auto[TlIntgErrCmd] | 105 | 1 | T249 | 10 | T250 | 3 | T251 | 7 | ||||
auto[TlIntgErrData] | 88 | 1 | T249 | 6 | T250 | 3 | T251 | 4 | ||||
auto[TlIntgErrBoth] | 97 | 1 | T249 | 4 | T250 | 4 | T251 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |