Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

19410615

1

T1

1467

T2

638

T3

576

full_word

6406572

1

T1

158

T2

141

T3

226

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	25816897	1			T1	1625		T2	779		T3	802
auto[TlIntgErrCmd]	102	1			T249	9		T250	3		T251	5
auto[TlIntgErrData]	94	1			T249	3		T250	4		T251	8
auto[TlIntgErrBoth]	94	1			T249	8		T250	3		T251	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7697322

1

T1

1565

T2

726

T3

516

auto[1]

18119865

1

T1

60

T2

53

T3

286

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4887177	1			T1	1435		T2	601		T3	401
auto[TlIntgErrNone]	partial	auto[1]	14523164	1			T1	32		T2	37		T3	175
auto[TlIntgErrNone]	full_word	auto[0]	2810015	1			T1	130		T2	125		T3	115
auto[TlIntgErrNone]	full_word	auto[1]	3596541	1			T1	28		T2	16		T3	111
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T249	6		T250	2		T251	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T249	3		T250	1		T251	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T375	1		T378	1		T256	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T377	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T249	3		T250	3		T251	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T250	1		T251	2		T372	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T251	1		T374	1		T379	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T251	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T249	3		T250	1		T251	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T249	5		T250	2		T251	6
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T373	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T372	1		T373	1		T374	1