Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	355202152	6130801	0	0
check_regwen_rd_A	355202152	2531	0	0
check_timeout_rd_A	355202152	2296	0	0
check_trigger_regwen_rd_A	355202152	2597	0	0
consistency_check_period_rd_A	355202152	2704	0	0
creator_sw_cfg_read_lock_rd_A	355202152	2299	0	0
direct_access_address_rd_A	355202152	2007	0	0
direct_access_wdata_0_rd_A	355202152	1252	0	0
direct_access_wdata_1_rd_A	355202152	1500	0	0
integrity_check_period_rd_A	355202152	2430	0	0
intr_enable_rd_A	355202152	3040	0	0
owner_sw_cfg_read_lock_rd_A	355202152	2264	0	0
rot_creator_auth_codesign_read_lock_rd_A	355202152	2542	0	0
rot_creator_auth_state_read_lock_rd_A	355202152	2339	0	0
vendor_test_read_lock_rd_A	355202152	2018	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	6130801	0	0
T6	785303	137854	0	0
T7	32337	0	0	0
T13	802285	66571	0	0
T14	0	44010	0	0
T15	150129	0	0	0
T16	0	45796	0	0
T17	0	43199	0	0
T27	0	284808	0	0
T48	11273	0	0	0
T49	9932	0	0	0
T50	13369	0	0	0
T65	0	158499	0	0
T109	28853	0	0	0
T110	12907	0	0	0
T257	15775	0	0	0
T258	0	36245	0	0
T259	0	93055	0	0
T260	0	179859	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2531	0	0
T14	238391	84	0	0
T17	0	127	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	43	0	0
T275	0	63	0	0
T341	0	44	0	0
T342	0	17	0	0
T343	0	27	0	0
T344	0	140	0	0
T345	0	68	0	0
T346	0	21	0	0
T347	31437	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2296	0	0
T14	238391	74	0	0
T17	0	73	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	57	0	0
T275	0	41	0	0
T341	0	91	0	0
T342	0	14	0	0
T343	0	66	0	0
T344	0	110	0	0
T345	0	86	0	0
T346	0	10	0	0
T347	31437	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2597	0	0
T14	238391	86	0	0
T17	0	63	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	54	0	0
T275	0	41	0	0
T341	0	27	0	0
T342	0	16	0	0
T343	0	48	0	0
T344	0	150	0	0
T345	0	80	0	0
T346	0	55	0	0
T347	31437	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2704	0	0
T14	238391	87	0	0
T17	0	67	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	41	0	0
T275	0	69	0	0
T341	0	46	0	0
T342	0	7	0	0
T343	0	71	0	0
T344	0	140	0	0
T345	0	131	0	0
T346	0	18	0	0
T347	31437	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2299	0	0
T14	238391	42	0	0
T17	0	77	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	79	0	0
T275	0	53	0	0
T341	0	56	0	0
T342	0	33	0	0
T343	0	58	0	0
T344	0	114	0	0
T345	0	96	0	0
T346	0	18	0	0
T347	31437	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2007	0	0
T14	238391	69	0	0
T17	0	104	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	59	0	0
T275	0	55	0	0
T341	0	61	0	0
T342	0	30	0	0
T343	0	67	0	0
T344	0	123	0	0
T345	0	120	0	0
T346	0	31	0	0
T347	31437	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	1252	0	0
T14	238391	30	0	0
T17	0	33	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	39	0	0
T275	0	21	0	0
T341	0	15	0	0
T342	0	9	0	0
T343	0	35	0	0
T344	0	117	0	0
T345	0	60	0	0
T346	0	30	0	0
T347	31437	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	1500	0	0
T14	238391	44	0	0
T17	0	35	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	24	0	0
T275	0	49	0	0
T341	0	17	0	0
T342	0	4	0	0
T343	0	41	0	0
T344	0	145	0	0
T345	0	35	0	0
T346	0	13	0	0
T347	31437	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2430	0	0
T14	238391	63	0	0
T17	0	53	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	46	0	0
T275	0	66	0	0
T341	0	40	0	0
T342	0	11	0	0
T343	0	65	0	0
T344	0	130	0	0
T345	0	132	0	0
T346	0	12	0	0
T347	31437	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	3040	0	0
T14	238391	56	0	0
T17	0	108	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T96	0	15	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T210	0	60	0	0
T223	19859	0	0	0
T258	0	45	0	0
T275	0	35	0	0
T341	0	56	0	0
T342	0	23	0	0
T343	0	56	0	0
T344	0	130	0	0
T347	31437	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2264	0	0
T14	238391	112	0	0
T17	0	95	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	62	0	0
T275	0	30	0	0
T341	0	69	0	0
T342	0	31	0	0
T343	0	31	0	0
T344	0	127	0	0
T345	0	115	0	0
T346	0	23	0	0
T347	31437	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2542	0	0
T14	238391	90	0	0
T17	0	114	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	81	0	0
T275	0	83	0	0
T341	0	21	0	0
T342	0	17	0	0
T343	0	100	0	0
T344	0	183	0	0
T345	0	85	0	0
T346	0	25	0	0
T347	31437	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2339	0	0
T14	238391	98	0	0
T17	0	97	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	49	0	0
T275	0	85	0	0
T341	0	30	0	0
T342	0	7	0	0
T343	0	49	0	0
T344	0	132	0	0
T345	0	106	0	0
T346	0	27	0	0
T347	31437	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355202152	2018	0	0
T14	238391	74	0	0
T17	0	61	0	0
T27	960088	0	0	0
T57	13064	0	0	0
T64	148674	0	0	0
T76	10223	0	0	0
T126	32075	0	0	0
T178	14753	0	0	0
T180	18449	0	0	0
T223	19859	0	0	0
T258	0	65	0	0
T275	0	64	0	0
T341	0	27	0	0
T342	0	24	0	0
T343	0	40	0	0
T344	0	98	0	0
T345	0	75	0	0
T346	0	31	0	0
T347	31437	0	0	0