Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.41	96.51	93.10		80.00	95.12	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.05	97.74	93.10	98.55	80.00	94.44	94.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	83	96.51
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	58	95.08
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	27	93.10
Logical	29	27	93.10
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T3,T5,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T3,T5,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10
1	1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T28

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T5,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T5,T8
ReadWaitSt	252	Covered	T3,T5,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T8
IdleSt->ReadSt	236	Covered	T3,T5,T8
InitSt->ErrorSt	315	Covered	T179
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T67,T113,T64
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T101,T28
ReadSt->ReadWaitSt	252	Covered	T3,T5,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T3,T5,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	3	75.00	(Not included in score)
Transitions	7	5	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T8,T101,T28
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T3,T5,T8
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T177,T180
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T101,T28,T29
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T3,T5,T8
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T8,T101,T28
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T3,T5,T10
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	39	95.12
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T5,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T13,T96
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T101,T28
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	24	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	24	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	352176410	351407570	0	0
DigestKnown_A	352176410	351407570	0	0
DigestOffsetMustBeRepresentable_A	1019	1019	0	0
EccErrorState_A	352176410	0	0	0
ErrorKnown_A	352176410	351407570	0	0
FsmStateKnown_A	352176410	351407570	0	0
InitDoneKnown_A	352176410	351407570	0	0
InitReadLocksPartition_A	352176410	69704281	0	0
InitWriteLocksPartition_A	352176410	69704281	0	0
OffsetMustBeBlockAligned_A	1019	1019	0	0
OtpAddrKnown_A	352176410	351407570	0	0
OtpCmdKnown_A	352176410	351407570	0	0
OtpErrorState_A	352176410	0	0	0
OtpReqKnown_A	352176410	351407570	0	0
OtpSizeKnown_A	352176410	351407570	0	0
OtpWdataKnown_A	352176410	351407570	0	0
ReadLockPropagation_A	352176410	156732090	0	0
SizeMustBeBlockAligned_A	1019	1019	0	0
TlulGntKnown_A	352176410	351407570	0	0
TlulRdataKnown_A	352176410	351407570	0	0
TlulReadOnReadLock_A	352176410	6375	0	0
TlulRerrorKnown_A	352176410	351407570	0	0
TlulRvalidKnown_A	352176410	351407570	0	0
WriteLockPropagation_A	352176410	1914451	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	352176410	22657383	0	0
u_state_regs_A	352176410	351407570	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	69704281	0	0
T1	25159	351	0	0
T2	27306	388	0	0
T3	11796	3025	0	0
T4	21479	1444	0	0
T5	34471	25035	0	0
T8	13641	5970	0	0
T9	12821	157	0	0
T10	25559	2187	0	0
T11	24911	349	0	0
T12	14235	3374	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	69704281	0	0
T1	25159	351	0	0
T2	27306	388	0	0
T3	11796	3025	0	0
T4	21479	1444	0	0
T5	34471	25035	0	0
T8	13641	5970	0	0
T9	12821	157	0	0
T10	25559	2187	0	0
T11	24911	349	0	0
T12	14235	3374	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	156732090	0	0
T4	21479	5468	0	0
T6	0	341602	0	0
T8	13641	5728	0	0
T9	12821	0	0	0
T10	25559	1208	0	0
T11	24911	0	0	0
T12	14235	0	0	0
T15	0	34239	0	0
T28	70759	6075	0	0
T29	0	4974	0	0
T39	0	13554	0	0
T66	12332	0	0	0
T67	0	6789	0	0
T101	12261	3557	0	0
T102	12855	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6375	0	0
T4	21479	0	0	0
T5	34471	27	0	0
T6	0	61	0	0
T8	13641	4	0	0
T9	12821	0	0	0
T10	25559	4	0	0
T11	24911	0	0	0
T12	14235	13	0	0
T28	70759	9	0	0
T29	0	4	0	0
T39	0	2	0	0
T66	12332	0	0	0
T67	0	11	0	0
T101	12261	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	1914451	0	0
T6	785303	0	0	0
T7	32337	0	0	0
T13	802285	0	0	0
T15	150129	0	0	0
T29	69629	658	0	0
T39	66253	7088	0	0
T48	11273	0	0	0
T49	9932	0	0	0
T64	0	101473	0	0
T67	35607	0	0	0
T75	0	11547	0	0
T96	0	247439	0	0
T97	0	7276	0	0
T103	10268	0	0	0
T104	0	14900	0	0
T107	0	2047	0	0
T108	0	19228	0	0
T174	0	30899	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	22657383	0	0
T4	21479	10308	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	4049	0	0
T15	0	74287	0	0
T28	70759	59964	0	0
T29	69629	60076	0	0
T39	0	47566	0	0
T64	0	908456	0	0
T66	12332	0	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T113	0	3530	0	0
T126	0	20481	0	0
T177	0	2924	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T66,T57,T76

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T28,T75,T30

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71,T138
1	Covered	T71,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T3,T5,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10
1	1	Covered	T2,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T28,T29

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T28,T29

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T5,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T5
ReadWaitSt	252	Covered	T2,T3,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T8
IdleSt->ReadSt	236	Covered	T2,T3,T5
InitSt->ErrorSt	315	Covered	T67,T113,T64
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T143,T156,T159
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T101,T28
ReadSt->ReadWaitSt	252	Covered	T2,T3,T5
ReadWaitSt->ErrorSt	276	Covered	T141,T142,T181
ReadWaitSt->IdleSt	270	Covered	T2,T3,T5
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T101,T28
CheckFailError	317	Covered	T71,T138
FsmStateError	289	Covered	T3,T5,T8
MacroEccCorrError	221	Covered	T28,T66,T57
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T15,T177
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T101,T28
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T71,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T5,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T66,T57,T76
MacroEccCorrError->NoError	235	Covered	T28,T75,T30
NoError->AccessError	256	Covered	T5,T101,T28
NoError->CheckFailError	317	Covered	T71,T138
NoError->FsmStateError	289	Covered	T3,T8,T10
NoError->MacroEccCorrError	221	Covered	T28,T66,T57

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T28,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T66,T57,T76
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T143,T156,T159
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T96,T182
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T101,T28
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T28,T75,T30
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T141,T142,T181
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71,T138
1	0	Covered	T71,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	352176410	351407570	0	0
DigestKnown_A	352176410	351407570	0	0
DigestOffsetMustBeRepresentable_A	1019	1019	0	0
EccErrorState_A	352176410	6431	0	0
ErrorKnown_A	352176410	351407570	0	0
FsmStateKnown_A	352176410	351407570	0	0
InitDoneKnown_A	352176410	351407570	0	0
InitReadLocksPartition_A	352176410	69866170	0	0
InitWriteLocksPartition_A	352176410	69866170	0	0
OffsetMustBeBlockAligned_A	1019	1019	0	0
OtpAddrKnown_A	352176410	351407570	0	0
OtpCmdKnown_A	352176410	351407570	0	0
OtpErrorState_A	352176410	59	0	0
OtpReqKnown_A	352176410	351407570	0	0
OtpSizeKnown_A	352176410	351407570	0	0
OtpWdataKnown_A	352176410	351407570	0	0
ReadLockPropagation_A	352176410	156678681	0	0
SizeMustBeBlockAligned_A	1019	1019	0	0
TlulGntKnown_A	352176410	351407570	0	0
TlulRdataKnown_A	352176410	351407570	0	0
TlulReadOnReadLock_A	352176410	6481	0	0
TlulRerrorKnown_A	352176410	351407570	0	0
TlulRvalidKnown_A	352176410	351407570	0	0
WriteLockPropagation_A	352176410	1997374	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	352176410	22486438	0	0
u_state_regs_A	352176410	351407570	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6431	0	0
T41	118131	0	0	0
T71	11531	3944	0	0
T78	12817	0	0	0
T86	34857	0	0	0
T87	23501	0	0	0
T88	69141	0	0	0
T89	189475	0	0	0
T90	31080	0	0	0
T138	0	2487	0	0
T145	12657	0	0	0
T146	84631	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	69866170	0	0
T1	25159	470	0	0
T2	27306	524	0	0
T3	11796	3059	0	0
T4	21479	1512	0	0
T5	34471	25086	0	0
T8	13641	6021	0	0
T9	12821	208	0	0
T10	25559	2306	0	0
T11	24911	451	0	0
T12	14235	3425	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	69866170	0	0
T1	25159	470	0	0
T2	27306	524	0	0
T3	11796	3059	0	0
T4	21479	1512	0	0
T5	34471	25086	0	0
T8	13641	6021	0	0
T9	12821	208	0	0
T10	25559	2306	0	0
T11	24911	451	0	0
T12	14235	3425	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	59	0	0
T54	15587	0	0	0
T96	262457	0	0	0
T97	61847	0	0	0
T141	0	1	0	0
T143	11832	1	0	0
T144	9982	0	0	0
T155	15203	0	0	0
T156	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T169	13024	0	0	0
T170	4342	0	0	0
T171	5493	0	0	0
T172	10402	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	156678681	0	0
T4	21479	5464	0	0
T5	34471	27002	0	0
T8	13641	5821	0	0
T9	12821	0	0	0
T10	25559	1206	0	0
T11	24911	0	0	0
T12	14235	5708	0	0
T28	70759	6546	0	0
T29	0	4363	0	0
T39	0	17095	0	0
T66	12332	0	0	0
T67	0	6780	0	0
T101	12261	3555	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6481	0	0
T4	21479	0	0	0
T5	34471	26	0	0
T6	0	48	0	0
T8	13641	8	0	0
T9	12821	0	0	0
T10	25559	1	0	0
T11	24911	0	0	0
T12	14235	9	0	0
T28	70759	16	0	0
T29	0	3	0	0
T39	0	3	0	0
T66	12332	0	0	0
T67	0	9	0	0
T101	12261	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	1997374	0	0
T4	21479	1700	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	0	0	0
T15	0	8201	0	0
T28	70759	4180	0	0
T29	69629	2397	0	0
T39	0	5563	0	0
T64	0	86502	0	0
T66	12332	0	0	0
T95	0	94898	0	0
T96	0	153586	0	0
T97	0	5397	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T126	0	3888	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	22486438	0	0
T4	21479	10274	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	0	0	0
T15	0	83694	0	0
T28	70759	59777	0	0
T29	69629	59838	0	0
T39	0	57826	0	0
T64	0	922667	0	0
T66	12332	0	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T113	0	3496	0	0
T126	0	20413	0	0
T177	0	2907	0	0
T178	0	4994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T74,T140

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T28,T137,T141

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71
1	Covered	T71

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T3,T5,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T4
1	1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111011000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T28,T66

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T28,T66

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T5,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T5,T4
ReadWaitSt	252	Covered	T3,T5,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T8
IdleSt->ReadSt	236	Covered	T3,T5,T4
InitSt->ErrorSt	315	Covered	T67,T113,T64
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T66,T143,T144
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T4,T12
ReadSt->ReadWaitSt	252	Covered	T3,T5,T4
ReadWaitSt->ErrorSt	276	Covered	T142,T183,T184
ReadWaitSt->IdleSt	270	Covered	T3,T5,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T4,T12
CheckFailError	317	Covered	T71
FsmStateError	289	Covered	T3,T5,T8
MacroEccCorrError	221	Covered	T3,T28,T137
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T12,T177
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T4,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T71
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T5,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T3,T137,T141
MacroEccCorrError->NoError	235	Covered	T28,T30,T185
NoError->AccessError	256	Covered	T5,T4,T12
NoError->CheckFailError	317	Covered	T71
NoError->FsmStateError	289	Covered	T8,T10,T28
NoError->MacroEccCorrError	221	Covered	T3,T28,T137

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T28,T66
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T3,T74,T140
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T66,T144,T157
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T5,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T96,T182
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T4,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T28,T137,T141
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T142,T183,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T8,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71
1	0	Covered	T71
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	352176410	351407570	0	0
DigestKnown_A	352176410	351407570	0	0
DigestOffsetMustBeRepresentable_A	1019	1019	0	0
EccErrorState_A	352176410	3944	0	0
ErrorKnown_A	352176410	351407570	0	0
FsmStateKnown_A	352176410	351407570	0	0
InitDoneKnown_A	352176410	351407570	0	0
InitReadLocksPartition_A	352176410	70026962	0	0
InitWriteLocksPartition_A	352176410	70026962	0	0
OffsetMustBeBlockAligned_A	1019	1019	0	0
OtpAddrKnown_A	352176410	351407570	0	0
OtpCmdKnown_A	352176410	351407570	0	0
OtpErrorState_A	352176410	51	0	0
OtpReqKnown_A	352176410	351407570	0	0
OtpSizeKnown_A	352176410	351407570	0	0
OtpWdataKnown_A	352176410	351407570	0	0
ReadLockPropagation_A	352176410	161803637	0	0
SizeMustBeBlockAligned_A	1019	1019	0	0
TlulGntKnown_A	352176410	351407570	0	0
TlulRdataKnown_A	352176410	351407570	0	0
TlulReadOnReadLock_A	352176410	6659	0	0
TlulRerrorKnown_A	352176410	351407570	0	0
TlulRvalidKnown_A	352176410	351407570	0	0
WriteLockPropagation_A	352176410	1158050	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	352176410	13487438	0	0
u_state_regs_A	352176410	351407570	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	3944	0	0
T41	118131	0	0	0
T71	11531	3944	0	0
T78	12817	0	0	0
T86	34857	0	0	0
T87	23501	0	0	0
T88	69141	0	0	0
T89	189475	0	0	0
T90	31080	0	0	0
T145	12657	0	0	0
T146	84631	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70026962	0	0
T1	25159	589	0	0
T2	27306	660	0	0
T3	11796	3093	0	0
T4	21479	1580	0	0
T5	34471	25137	0	0
T8	13641	6072	0	0
T9	12821	259	0	0
T10	25559	2425	0	0
T11	24911	553	0	0
T12	14235	3476	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70026962	0	0
T1	25159	589	0	0
T2	27306	660	0	0
T3	11796	3093	0	0
T4	21479	1580	0	0
T5	34471	25137	0	0
T8	13641	6072	0	0
T9	12821	259	0	0
T10	25559	2425	0	0
T11	24911	553	0	0
T12	14235	3476	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	51	0	0
T6	785303	0	0	0
T7	32337	0	0	0
T15	150129	0	0	0
T29	69629	0	0	0
T39	66253	0	0	0
T48	11273	0	0	0
T66	12332	1	0	0
T67	35607	0	0	0
T92	0	1	0	0
T102	12855	0	0	0
T103	10268	0	0	0
T142	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	161803637	0	0
T4	21479	5460	0	0
T5	34471	27307	0	0
T6	0	294384	0	0
T8	13641	0	0	0
T9	12821	0	0	0
T10	25559	1648	0	0
T11	24911	0	0	0
T12	14235	5284	0	0
T15	0	5656	0	0
T28	70759	7681	0	0
T29	0	3772	0	0
T39	0	10151	0	0
T66	12332	0	0	0
T101	12261	3553	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6659	0	0
T4	21479	2	0	0
T5	34471	21	0	0
T6	0	47	0	0
T7	0	17	0	0
T8	13641	7	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	17	0	0
T28	70759	15	0	0
T29	0	3	0	0
T66	12332	0	0	0
T67	0	7	0	0
T101	12261	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	1158050	0	0
T6	785303	0	0	0
T7	32337	0	0	0
T15	0	12052	0	0
T28	70759	5280	0	0
T29	69629	0	0	0
T39	66253	9874	0	0
T48	11273	0	0	0
T64	0	58599	0	0
T66	12332	0	0	0
T67	35607	0	0	0
T75	0	11547	0	0
T96	0	19554	0	0
T97	0	2354	0	0
T100	0	7585	0	0
T102	12855	0	0	0
T103	10268	0	0	0
T106	0	23365	0	0
T108	0	7447	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	13487438	0	0
T6	785303	0	0	0
T12	14235	3981	0	0
T15	0	70451	0	0
T28	70759	59590	0	0
T29	69629	0	0	0
T39	66253	57656	0	0
T64	0	728603	0	0
T66	12332	3465	0	0
T67	35607	0	0	0
T96	0	389841	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T103	10268	0	0	0
T113	0	3462	0	0
T144	0	2845	0	0
T177	0	2890	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0