Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.79		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T74,T136

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T28,T137,T75

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71,T138
1	Covered	T71,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T3,T5,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T4
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T28

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T5,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T8
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T67,T113,T64
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T66,T144,T155
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T4,T101
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T141,T186,T187
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T4,T101
CheckFailError	317	Covered	T71,T138
FsmStateError	289	Covered	T3,T5,T8
MacroEccCorrError	221	Covered	T28,T58,T137
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T101,T28
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T71,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T5,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T58,T137,T141
MacroEccCorrError->NoError	235	Covered	T28,T75,T30
NoError->AccessError	256	Covered	T5,T4,T101
NoError->CheckFailError	317	Covered	T71,T138
NoError->FsmStateError	289	Covered	T3,T8,T10
NoError->MacroEccCorrError	221	Covered	T28,T58,T137

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T58,T74,T136
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T155,T140,T188
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T96,T182
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T4,T101
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T28,T137,T75
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T141,T186,T187
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71,T138
1	0	Covered	T71,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	352176410	351407570	0	0
DigestKnown_A	352176410	351407570	0	0
DigestOffsetMustBeRepresentable_A	1019	1019	0	0
EccErrorState_A	352176410	6431	0	0
ErrorKnown_A	352176410	351407570	0	0
FsmStateKnown_A	352176410	351407570	0	0
InitDoneKnown_A	352176410	351407570	0	0
InitReadLocksPartition_A	352176410	70186943	0	0
InitWriteLocksPartition_A	352176410	70186943	0	0
OffsetMustBeBlockAligned_A	1019	1019	0	0
OtpAddrKnown_A	352176410	351407570	0	0
OtpCmdKnown_A	352176410	351407570	0	0
OtpErrorState_A	352176410	41	0	0
OtpReqKnown_A	352176410	351407570	0	0
OtpSizeKnown_A	352176410	351407570	0	0
OtpWdataKnown_A	352176410	351407570	0	0
ReadLockPropagation_A	352176410	163250377	0	0
SizeMustBeBlockAligned_A	1019	1019	0	0
TlulGntKnown_A	352176410	351407570	0	0
TlulRdataKnown_A	352176410	351407570	0	0
TlulReadOnReadLock_A	352176410	6457	0	0
TlulRerrorKnown_A	352176410	351407570	0	0
TlulRvalidKnown_A	352176410	351407570	0	0
WriteLockPropagation_A	352176410	2142465	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	352176410	23049370	0	0
u_state_regs_A	352176410	351407570	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6431	0	0
T41	118131	0	0	0
T71	11531	3944	0	0
T78	12817	0	0	0
T86	34857	0	0	0
T87	23501	0	0	0
T88	69141	0	0	0
T89	189475	0	0	0
T90	31080	0	0	0
T138	0	2487	0	0
T145	12657	0	0	0
T146	84631	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70186943	0	0
T1	25159	708	0	0
T2	27306	796	0	0
T3	11796	3127	0	0
T4	21479	1648	0	0
T5	34471	25188	0	0
T8	13641	6123	0	0
T9	12821	310	0	0
T10	25559	2544	0	0
T11	24911	655	0	0
T12	14235	3527	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70186943	0	0
T1	25159	708	0	0
T2	27306	796	0	0
T3	11796	3127	0	0
T4	21479	1648	0	0
T5	34471	25188	0	0
T8	13641	6123	0	0
T9	12821	310	0	0
T10	25559	2544	0	0
T11	24911	655	0	0
T12	14235	3527	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	41	0	0
T17	264174	0	0	0
T33	9126	0	0	0
T98	27809	0	0	0
T105	33860	0	0	0
T137	86145	0	0	0
T140	0	1	0	0
T141	0	1	0	0
T155	15203	1	0	0
T173	25007	0	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	31162	0	0	0
T195	38610	0	0	0
T196	16129	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	163250377	0	0
T4	21479	5621	0	0
T5	34471	27000	0	0
T6	0	346079	0	0
T8	13641	5724	0	0
T9	12821	0	0	0
T10	25559	1202	0	0
T11	24911	0	0	0
T12	14235	4085	0	0
T28	70759	7107	0	0
T29	0	3514	0	0
T39	0	13756	0	0
T66	12332	0	0	0
T101	12261	1475	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6457	0	0
T4	21479	2	0	0
T5	34471	19	0	0
T8	13641	3	0	0
T9	12821	0	0	0
T10	25559	2	0	0
T11	24911	0	0	0
T12	14235	6	0	0
T28	70759	13	0	0
T29	0	4	0	0
T39	0	2	0	0
T66	12332	0	0	0
T67	0	7	0	0
T101	12261	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	2142465	0	0
T6	785303	0	0	0
T7	32337	0	0	0
T13	802285	0	0	0
T15	150129	5877	0	0
T29	69629	2160	0	0
T39	66253	3857	0	0
T48	11273	0	0	0
T49	9932	0	0	0
T64	0	122357	0	0
T67	35607	0	0	0
T95	0	94898	0	0
T96	0	150667	0	0
T97	0	2557	0	0
T100	0	7454	0	0
T103	10268	0	0	0
T104	0	14455	0	0
T105	0	4626	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	23049370	0	0
T4	21479	4131	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	3947	0	0
T15	0	60704	0	0
T28	70759	59403	0	0
T29	69629	59362	0	0
T39	0	47158	0	0
T64	0	926944	0	0
T66	12332	0	0	0
T67	0	2543	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T113	0	3428	0	0
T177	0	2873	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T114,T74

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T28,T139,T75

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T138
1	Covered	T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T3,T5,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10
1	1	Covered	T3,T5,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T5,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T5,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T29,T67

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T29,T67

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T5,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T5,T4
ReadWaitSt	252	Covered	T3,T5,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T5,T8
IdleSt->ReadSt	236	Covered	T3,T5,T4
InitSt->ErrorSt	315	Covered	T66,T67,T113
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T155,T197,T140
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T28,T29
ReadSt->ReadWaitSt	252	Covered	T3,T5,T4
ReadWaitSt->ErrorSt	276	Covered	T137,T141,T142
ReadWaitSt->IdleSt	270	Covered	T3,T5,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T28,T29
CheckFailError	317	Covered	T138
FsmStateError	289	Covered	T3,T5,T8
MacroEccCorrError	221	Covered	T28,T58,T139
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T28,T29,T67
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T5,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T58,T114,T74
MacroEccCorrError->NoError	235	Covered	T28,T139,T75
NoError->AccessError	256	Covered	T5,T28,T29
NoError->CheckFailError	317	Covered	T138
NoError->FsmStateError	289	Covered	T3,T8,T10
NoError->MacroEccCorrError	221	Covered	T28,T58,T139

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T67
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T58,T114,T74
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T197,T136,T198
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T5,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T13,T96
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T28,T29
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T28,T139,T75
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T137,T141,T142
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T8,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T138
1	0	Covered	T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	352176410	351407570	0	0
DigestKnown_A	352176410	351407570	0	0
DigestOffsetMustBeRepresentable_A	1019	1019	0	0
EccErrorState_A	352176410	2487	0	0
ErrorKnown_A	352176410	351407570	0	0
FsmStateKnown_A	352176410	351407570	0	0
InitDoneKnown_A	352176410	351407570	0	0
InitReadLocksPartition_A	352176410	70346210	0	0
InitWriteLocksPartition_A	352176410	70346210	0	0
OffsetMustBeBlockAligned_A	1019	1019	0	0
OtpAddrKnown_A	352176410	351407570	0	0
OtpCmdKnown_A	352176410	351407570	0	0
OtpErrorState_A	352176410	31	0	0
OtpReqKnown_A	352176410	351407570	0	0
OtpSizeKnown_A	352176410	351407570	0	0
OtpWdataKnown_A	352176410	351407570	0	0
ReadLockPropagation_A	352176410	155706259	0	0
SizeMustBeBlockAligned_A	1019	1019	0	0
TlulGntKnown_A	352176410	351407570	0	0
TlulRdataKnown_A	352176410	351407570	0	0
TlulReadOnReadLock_A	352176410	6156	0	0
TlulRerrorKnown_A	352176410	351407570	0	0
TlulRvalidKnown_A	352176410	351407570	0	0
WriteLockPropagation_A	352176410	833331	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	352176410	10470131	0	0
u_state_regs_A	352176410	351407570	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	2487	0	0
T62	12061	0	0	0
T138	14593	2487	0	0
T147	61968	0	0	0
T148	14718	0	0	0
T149	10479	0	0	0
T150	53616	0	0	0
T151	19685	0	0	0
T152	16143	0	0	0
T153	19450	0	0	0
T154	120690	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70346210	0	0
T1	25159	827	0	0
T2	27306	932	0	0
T3	11796	3161	0	0
T4	21479	1716	0	0
T5	34471	25239	0	0
T8	13641	6174	0	0
T9	12821	361	0	0
T10	25559	2663	0	0
T11	24911	757	0	0
T12	14235	3578	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	70346210	0	0
T1	25159	827	0	0
T2	27306	932	0	0
T3	11796	3161	0	0
T4	21479	1716	0	0
T5	34471	25239	0	0
T8	13641	6174	0	0
T9	12821	361	0	0
T10	25559	2663	0	0
T11	24911	757	0	0
T12	14235	3578	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	31	0	0
T93	0	1	0	0
T99	20741	0	0	0
T100	74956	0	0	0
T136	0	1	0	0
T137	86145	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T194	31162	0	0	0
T195	38610	0	0	0
T196	16129	0	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	45355	0	0	0
T203	20148	0	0	0
T204	37014	0	0	0
T205	75834	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	155706259	0	0
T4	21479	4007	0	0
T5	34471	26998	0	0
T8	13641	5722	0	0
T9	12821	0	0	0
T10	25559	1646	0	0
T11	24911	0	0	0
T12	14235	5706	0	0
T28	70759	8176	0	0
T29	0	3822	0	0
T39	0	14557	0	0
T66	12332	0	0	0
T67	0	6775	0	0
T101	12261	3277	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	6156	0	0
T4	21479	0	0	0
T5	34471	26	0	0
T6	0	42	0	0
T7	0	18	0	0
T8	13641	3	0	0
T9	12821	0	0	0
T10	25559	2	0	0
T11	24911	0	0	0
T12	14235	11	0	0
T28	70759	10	0	0
T29	0	3	0	0
T39	0	1	0	0
T66	12332	0	0	0
T67	0	8	0	0
T101	12261	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	833331	0	0
T6	785303	0	0	0
T7	32337	0	0	0
T13	802285	0	0	0
T15	150129	0	0	0
T29	69629	2691	0	0
T39	66253	0	0	0
T48	11273	0	0	0
T49	9932	0	0	0
T64	0	16332	0	0
T67	35607	0	0	0
T96	0	35031	0	0
T103	10268	0	0	0
T104	0	15261	0	0
T116	0	5455	0	0
T175	0	22798	0	0
T176	0	12690	0	0
T206	0	45356	0	0
T207	0	14565	0	0
T208	0	19870	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	10470131	0	0
T4	21479	10172	0	0
T9	12821	0	0	0
T10	25559	0	0	0
T11	24911	0	0	0
T12	14235	0	0	0
T15	0	4105	0	0
T28	70759	0	0	0
T29	69629	59124	0	0
T64	0	226248	0	0
T66	12332	0	0	0
T67	0	2526	0	0
T95	0	100911	0	0
T96	0	133466	0	0
T101	12261	0	0	0
T102	12855	0	0	0
T104	0	153600	0	0
T126	0	20209	0	0
T178	0	4943	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352176410	351407570	0	0
T1	25159	24633	0	0
T2	27306	26801	0	0
T3	11796	11594	0	0
T4	21479	21139	0	0
T5	34471	34236	0	0
T8	13641	13395	0	0
T9	12821	12575	0	0
T10	25559	24942	0	0
T11	24911	24433	0	0
T12	14235	14010	0	0