SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.97 | 100.00 | 71.88 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
98.68 | 100.00 | 94.74 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
96.83 | 100.00 | 92.31 | 95.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.14 | 94.16 | 96.15 | 96.79 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 93.64 | 100.00 | 90.00 | 90.91 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.36 | 95.00 | 87.10 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.36 | 95.00 | 87.10 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.37 | 95.00 | 89.47 | 85.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.64 | 100.00 | 94.55 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.58 | 92.00 | 80.00 | 72.73 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
98.68 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T9 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
98.68 | 94.74 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
98.68 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 6 | 6 | 100.00 | 6 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 6 | 6 | 100.00 | 6 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 2147483647 | 221704482 | 0 | 0 |
DepthKnown_A | 2147483647 | 2147483647 | 0 | 0 |
RvalidKnown_A | 2147483647 | 2147483647 | 0 | 0 |
WreadyKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 1408705640 | 34387134 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 7164 | 7164 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 221704482 | 0 | 0 |
T1 | 251590 | 14671 | 0 | 0 |
T2 | 273060 | 10785 | 0 | 0 |
T3 | 117960 | 6388 | 0 | 0 |
T4 | 214790 | 22546 | 0 | 0 |
T5 | 344710 | 57906 | 0 | 0 |
T8 | 136410 | 12380 | 0 | 0 |
T9 | 128210 | 9729 | 0 | 0 |
T10 | 255590 | 17383 | 0 | 0 |
T11 | 249110 | 27221 | 0 | 0 |
T12 | 142350 | 16302 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 251590 | 246330 | 0 | 0 |
T2 | 273060 | 268010 | 0 | 0 |
T3 | 117960 | 115940 | 0 | 0 |
T4 | 214790 | 211390 | 0 | 0 |
T5 | 344710 | 342360 | 0 | 0 |
T8 | 136410 | 133950 | 0 | 0 |
T9 | 128210 | 125750 | 0 | 0 |
T10 | 255590 | 249420 | 0 | 0 |
T11 | 249110 | 244330 | 0 | 0 |
T12 | 142350 | 140100 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 251590 | 246330 | 0 | 0 |
T2 | 273060 | 268010 | 0 | 0 |
T3 | 117960 | 115940 | 0 | 0 |
T4 | 214790 | 211390 | 0 | 0 |
T5 | 344710 | 342360 | 0 | 0 |
T8 | 136410 | 133950 | 0 | 0 |
T9 | 128210 | 125750 | 0 | 0 |
T10 | 255590 | 249420 | 0 | 0 |
T11 | 249110 | 244330 | 0 | 0 |
T12 | 142350 | 140100 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 251590 | 246330 | 0 | 0 |
T2 | 273060 | 268010 | 0 | 0 |
T3 | 117960 | 115940 | 0 | 0 |
T4 | 214790 | 211390 | 0 | 0 |
T5 | 344710 | 342360 | 0 | 0 |
T8 | 136410 | 133950 | 0 | 0 |
T9 | 128210 | 125750 | 0 | 0 |
T10 | 255590 | 249420 | 0 | 0 |
T11 | 249110 | 244330 | 0 | 0 |
T12 | 142350 | 140100 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1408705640 | 34387134 | 0 | 0 |
T1 | 100636 | 8171 | 0 | 0 |
T2 | 109224 | 7661 | 0 | 0 |
T3 | 47184 | 3062 | 0 | 0 |
T4 | 85916 | 6242 | 0 | 0 |
T5 | 137884 | 3742 | 0 | 0 |
T8 | 54564 | 2908 | 0 | 0 |
T9 | 51284 | 3709 | 0 | 0 |
T10 | 102236 | 7571 | 0 | 0 |
T11 | 99644 | 9433 | 0 | 0 |
T12 | 56940 | 3622 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7164 | 7164 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 352176410 | 15369205 | 0 | 0 |
DepthKnown_A | 352176410 | 351407570 | 0 | 0 |
RvalidKnown_A | 352176410 | 351407570 | 0 | 0 |
WreadyKnown_A | 352176410 | 351407570 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 352176410 | 15369205 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 15369205 | 0 | 0 |
T1 | 25159 | 8129 | 0 | 0 |
T2 | 27306 | 7632 | 0 | 0 |
T3 | 11796 | 2482 | 0 | 0 |
T4 | 21479 | 6104 | 0 | 0 |
T5 | 34471 | 3238 | 0 | 0 |
T8 | 13641 | 2833 | 0 | 0 |
T9 | 12821 | 3655 | 0 | 0 |
T10 | 25559 | 7523 | 0 | 0 |
T11 | 24911 | 8782 | 0 | 0 |
T12 | 14235 | 3412 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 15369205 | 0 | 0 |
T1 | 25159 | 8129 | 0 | 0 |
T2 | 27306 | 7632 | 0 | 0 |
T3 | 11796 | 2482 | 0 | 0 |
T4 | 21479 | 6104 | 0 | 0 |
T5 | 34471 | 3238 | 0 | 0 |
T8 | 13641 | 2833 | 0 | 0 |
T9 | 12821 | 3655 | 0 | 0 |
T10 | 25559 | 7523 | 0 | 0 |
T11 | 24911 | 8782 | 0 | 0 |
T12 | 14235 | 3412 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 49217869 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 49217869 | 0 | 0 |
T1 | 25159 | 1625 | 0 | 0 |
T2 | 27306 | 779 | 0 | 0 |
T3 | 11796 | 802 | 0 | 0 |
T4 | 21479 | 4076 | 0 | 0 |
T5 | 34471 | 13541 | 0 | 0 |
T8 | 13641 | 2368 | 0 | 0 |
T9 | 12821 | 533 | 0 | 0 |
T10 | 25559 | 2453 | 0 | 0 |
T11 | 24911 | 4447 | 0 | 0 |
T12 | 14235 | 3170 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 48369560 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 48369560 | 0 | 0 |
T1 | 25159 | 1625 | 0 | 0 |
T2 | 27306 | 783 | 0 | 0 |
T3 | 11796 | 861 | 0 | 0 |
T4 | 21479 | 4076 | 0 | 0 |
T5 | 34471 | 13541 | 0 | 0 |
T8 | 13641 | 2368 | 0 | 0 |
T9 | 12821 | 2477 | 0 | 0 |
T10 | 25559 | 2453 | 0 | 0 |
T11 | 24911 | 4447 | 0 | 0 |
T12 | 14235 | 3170 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 20657963 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 20657963 | 0 | 0 |
T1 | 25159 | 2 | 0 | 0 |
T2 | 27306 | 1 | 0 | 0 |
T3 | 11796 | 22 | 0 | 0 |
T4 | 21479 | 10 | 0 | 0 |
T5 | 34471 | 126 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 2 | 0 | 0 |
T10 | 25559 | 10 | 0 | 0 |
T11 | 24911 | 31 | 0 | 0 |
T12 | 14235 | 58 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 17831052 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 17831052 | 0 | 0 |
T1 | 25159 | 2 | 0 | 0 |
T2 | 27306 | 5 | 0 | 0 |
T3 | 11796 | 81 | 0 | 0 |
T4 | 21479 | 10 | 0 | 0 |
T5 | 34471 | 126 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 8 | 0 | 0 |
T10 | 25559 | 10 | 0 | 0 |
T11 | 24911 | 31 | 0 | 0 |
T12 | 14235 | 58 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 20702396 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 20702396 | 0 | 0 |
T1 | 25159 | 1623 | 0 | 0 |
T2 | 27306 | 778 | 0 | 0 |
T3 | 11796 | 780 | 0 | 0 |
T4 | 21479 | 4066 | 0 | 0 |
T5 | 34471 | 13415 | 0 | 0 |
T8 | 13641 | 2343 | 0 | 0 |
T9 | 12821 | 531 | 0 | 0 |
T10 | 25559 | 2443 | 0 | 0 |
T11 | 24911 | 4416 | 0 | 0 |
T12 | 14235 | 3112 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 355202152 | 30538508 | 0 | 0 |
DepthKnown_A | 355202152 | 354381581 | 0 | 0 |
RvalidKnown_A | 355202152 | 354381581 | 0 | 0 |
WreadyKnown_A | 355202152 | 354381581 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1194 | 1194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 30538508 | 0 | 0 |
T1 | 25159 | 1623 | 0 | 0 |
T2 | 27306 | 778 | 0 | 0 |
T3 | 11796 | 780 | 0 | 0 |
T4 | 21479 | 4066 | 0 | 0 |
T5 | 34471 | 13415 | 0 | 0 |
T8 | 13641 | 2343 | 0 | 0 |
T9 | 12821 | 2469 | 0 | 0 |
T10 | 25559 | 2443 | 0 | 0 |
T11 | 24911 | 4416 | 0 | 0 |
T12 | 14235 | 3112 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 355202152 | 354381581 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1194 | 1194 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 352176410 | 18263523 | 0 | 0 |
DepthKnown_A | 352176410 | 351407570 | 0 | 0 |
RvalidKnown_A | 352176410 | 351407570 | 0 | 0 |
WreadyKnown_A | 352176410 | 351407570 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 352176410 | 18263523 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 18263523 | 0 | 0 |
T1 | 25159 | 20 | 0 | 0 |
T2 | 27306 | 14 | 0 | 0 |
T3 | 11796 | 279 | 0 | 0 |
T4 | 21479 | 64 | 0 | 0 |
T5 | 34471 | 189 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 26 | 0 | 0 |
T10 | 25559 | 19 | 0 | 0 |
T11 | 24911 | 310 | 0 | 0 |
T12 | 14235 | 76 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 18263523 | 0 | 0 |
T1 | 25159 | 20 | 0 | 0 |
T2 | 27306 | 14 | 0 | 0 |
T3 | 11796 | 279 | 0 | 0 |
T4 | 21479 | 64 | 0 | 0 |
T5 | 34471 | 189 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 26 | 0 | 0 |
T10 | 25559 | 19 | 0 | 0 |
T11 | 24911 | 310 | 0 | 0 |
T12 | 14235 | 76 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T2,T3 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 352176410 | 542290 | 0 | 0 |
DepthKnown_A | 352176410 | 351407570 | 0 | 0 |
RvalidKnown_A | 352176410 | 351407570 | 0 | 0 |
WreadyKnown_A | 352176410 | 351407570 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 352176410 | 542290 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 542290 | 0 | 0 |
T1 | 25159 | 20 | 0 | 0 |
T2 | 27306 | 10 | 0 | 0 |
T3 | 11796 | 220 | 0 | 0 |
T4 | 21479 | 64 | 0 | 0 |
T5 | 34471 | 189 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 20 | 0 | 0 |
T10 | 25559 | 19 | 0 | 0 |
T11 | 24911 | 310 | 0 | 0 |
T12 | 14235 | 76 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 542290 | 0 | 0 |
T1 | 25159 | 20 | 0 | 0 |
T2 | 27306 | 10 | 0 | 0 |
T3 | 11796 | 220 | 0 | 0 |
T4 | 21479 | 64 | 0 | 0 |
T5 | 34471 | 189 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 20 | 0 | 0 |
T10 | 25559 | 19 | 0 | 0 |
T11 | 24911 | 310 | 0 | 0 |
T12 | 14235 | 76 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 18 | 18 | 100.00 |
Logical | 18 | 18 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T2,T3,T9 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Covered | T1,T2,T3 | |
1 | 1 | Covered | T1,T2,T3 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 352176410 | 212116 | 0 | 0 |
DepthKnown_A | 352176410 | 351407570 | 0 | 0 |
RvalidKnown_A | 352176410 | 351407570 | 0 | 0 |
WreadyKnown_A | 352176410 | 351407570 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 352176410 | 212116 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 212116 | 0 | 0 |
T1 | 25159 | 2 | 0 | 0 |
T2 | 27306 | 5 | 0 | 0 |
T3 | 11796 | 81 | 0 | 0 |
T4 | 21479 | 10 | 0 | 0 |
T5 | 34471 | 126 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 8 | 0 | 0 |
T10 | 25559 | 10 | 0 | 0 |
T11 | 24911 | 31 | 0 | 0 |
T12 | 14235 | 58 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 351407570 | 0 | 0 |
T1 | 25159 | 24633 | 0 | 0 |
T2 | 27306 | 26801 | 0 | 0 |
T3 | 11796 | 11594 | 0 | 0 |
T4 | 21479 | 21139 | 0 | 0 |
T5 | 34471 | 34236 | 0 | 0 |
T8 | 13641 | 13395 | 0 | 0 |
T9 | 12821 | 12575 | 0 | 0 |
T10 | 25559 | 24942 | 0 | 0 |
T11 | 24911 | 24433 | 0 | 0 |
T12 | 14235 | 14010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 352176410 | 212116 | 0 | 0 |
T1 | 25159 | 2 | 0 | 0 |
T2 | 27306 | 5 | 0 | 0 |
T3 | 11796 | 81 | 0 | 0 |
T4 | 21479 | 10 | 0 | 0 |
T5 | 34471 | 126 | 0 | 0 |
T8 | 13641 | 25 | 0 | 0 |
T9 | 12821 | 8 | 0 | 0 |
T10 | 25559 | 10 | 0 | 0 |
T11 | 24911 | 31 | 0 | 0 |
T12 | 14235 | 58 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |