SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 69.44 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
buf_err_code_cg_wrap[OtpSecret0ErrIdx] | 0.00 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
fsm_err | 0 | 1 | 1 | |
check_fail | 0 | 1 | 1 | |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 | |
no_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113119 | 1 | T2 | 1 | T4 | 54 | T5 | 51 | ||||
check_fail | 5 | 1 | T64 | 1 | T65 | 1 | T66 | 1 | ||||
ecc_uncorr_err | 46 | 1 | T22 | 1 | T125 | 1 | T32 | 1 | ||||
ecc_corr_err | 55 | 1 | T34 | 2 | T62 | 40 | T63 | 13 | ||||
no_err | 148273 | 1 | T4 | 421 | T5 | 28 | T8 | 626 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113073 | 1 | T1 | 1 | T4 | 54 | T5 | 51 | ||||
check_fail | 3 | 1 | T37 | 1 | T38 | 1 | T39 | 1 | ||||
ecc_uncorr_err | 99 | 1 | T59 | 1 | T43 | 42 | T79 | 1 | ||||
ecc_corr_err | 61 | 1 | T34 | 3 | T35 | 55 | T36 | 3 | ||||
no_err | 148197 | 1 | T4 | 421 | T5 | 28 | T8 | 626 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113053 | 1 | T2 | 1 | T4 | 54 | T5 | 51 | ||||
check_fail | 13 | 1 | T28 | 1 | T29 | 1 | T30 | 1 | ||||
ecc_uncorr_err | 111 | 1 | T43 | 42 | T115 | 1 | T55 | 1 | ||||
ecc_corr_err | 26 | 1 | T26 | 20 | T27 | 6 | - | - | ||||
no_err | 148516 | 1 | T4 | 421 | T5 | 28 | T8 | 626 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113074 | 1 | T4 | 54 | T5 | 51 | T6 | 53 | ||||
check_fail | 22 | 1 | T46 | 1 | T47 | 1 | T48 | 1 | ||||
ecc_uncorr_err | 39 | 1 | T2 | 1 | T80 | 1 | T81 | 1 | ||||
ecc_corr_err | 447 | 1 | T43 | 42 | T44 | 38 | T45 | 23 | ||||
no_err | 148029 | 1 | T4 | 421 | T5 | 28 | T8 | 626 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113004 | 1 | T1 | 1 | T2 | 1 | T4 | 54 | ||||
check_fail | 18 | 1 | T51 | 1 | T52 | 1 | T53 | 1 | ||||
ecc_uncorr_err | 137 | 1 | T41 | 1 | T23 | 1 | T24 | 1 | ||||
ecc_corr_err | 63 | 1 | T50 | 60 | T36 | 3 | - | - | ||||
no_err | 148339 | 1 | T4 | 421 | T5 | 28 | T8 | 626 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |