SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
85.71 | 80.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] | 57.14 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
57.14 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 3 | 4 | 57.14 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 3 | 4 | 57.14 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 3 | 4 | 57.14 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 113014 | 1 | T4 | 54 | T5 | 51 | T6 | 53 | ||||
check_fail | 5 | 1 | T171 | 1 | T172 | 1 | T169 | 1 | ||||
access_err | 50546 | 1 | T4 | 174 | T8 | 239 | T6 | 34 | ||||
no_err | 98380 | 1 | T4 | 247 | T5 | 28 | T8 | 387 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 112435 | 1 | T1 | 1 | T4 | 54 | T5 | 51 | ||||
check_fail | 6 | 1 | T77 | 1 | T171 | 1 | T174 | 1 | ||||
access_err | 49070 | 1 | T4 | 364 | T8 | 241 | T6 | 37 | ||||
ecc_uncorr_err | 685 | 1 | T108 | 11 | T121 | 1 | T175 | 1 | ||||
ecc_corr_err | 737 | 1 | T108 | 2 | T50 | 6 | T43 | 77 | ||||
no_err | 99012 | 1 | T4 | 57 | T5 | 28 | T8 | 385 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 112684 | 1 | T1 | 1 | T2 | 1 | T4 | 54 | ||||
check_fail | 5 | 1 | T77 | 1 | T159 | 1 | T171 | 1 | ||||
access_err | 48572 | 1 | T4 | 280 | T5 | 4 | T8 | 230 | ||||
ecc_uncorr_err | 465 | 1 | T167 | 56 | T196 | 1 | T197 | 1 | ||||
ecc_corr_err | 775 | 1 | T5 | 14 | T108 | 22 | T50 | 85 | ||||
no_err | 99402 | 1 | T4 | 141 | T5 | 10 | T8 | 396 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 112618 | 1 | T4 | 54 | T5 | 51 | T6 | 53 | ||||
check_fail | 2 | 1 | T169 | 1 | T170 | 1 | - | - | ||||
access_err | 49662 | 1 | T4 | 304 | T5 | 7 | T8 | 216 | ||||
ecc_uncorr_err | 498 | 1 | T1 | 1 | T173 | 1 | T227 | 1 | ||||
ecc_corr_err | 739 | 1 | T10 | 9 | T108 | 1 | T50 | 49 | ||||
no_err | 98281 | 1 | T4 | 117 | T5 | 21 | T8 | 410 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 112114 | 1 | T1 | 1 | T4 | 54 | T5 | 51 | ||||
check_fail | 7 | 1 | T159 | 1 | T171 | 1 | T174 | 1 | ||||
access_err | 49879 | 1 | T4 | 271 | T8 | 155 | T6 | 20 | ||||
ecc_uncorr_err | 1013 | 1 | T67 | 1 | T114 | 1 | T245 | 1 | ||||
ecc_corr_err | 884 | 1 | T10 | 23 | T108 | 1 | T50 | 27 | ||||
no_err | 97850 | 1 | T4 | 150 | T5 | 28 | T8 | 471 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |