Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23419430

1

T1

439

T2

1056

T3

7502

full_word

7732738

1

T1

190

T2

294

T3

5351

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31151838	1			T1	629		T2	1350		T3	12853
auto[TlIntgErrCmd]	115	1			T284	3		T285	4		T286	3
auto[TlIntgErrData]	98	1			T284	5		T285	10		T286	1
auto[TlIntgErrBoth]	117	1			T284	12		T285	6		T286	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9278648

1

T1

400

T2

1035

T3

5209

auto[1]

21873520

1

T1

229

T2

315

T3

7644

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5884385	1			T1	305		T2	873		T3	3481
auto[TlIntgErrNone]	partial	auto[1]	17534759	1			T1	134		T2	183		T3	4021
auto[TlIntgErrNone]	full_word	auto[0]	3394120	1			T1	95		T2	162		T3	1728
auto[TlIntgErrNone]	full_word	auto[1]	4338574	1			T1	95		T2	132		T3	3623
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T284	1		T285	1		T286	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T284	2		T285	3		T286	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T399	1		T405	1		T400	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T400	1		T402	2		T404	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T284	1		T285	3		T405	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T284	4		T285	5		T399	6
auto[TlIntgErrData]	full_word	auto[0]	2	1			T399	1		T406	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	10	1			T285	2		T286	1		T405	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T284	6		T285	1		T286	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T284	4		T285	3		T286	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T399	1		T407	2		T408	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T284	2		T285	2		T399	1