Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	441261928	7400755	0	0
check_regwen_rd_A	441261928	3091	0	0
check_timeout_rd_A	441261928	2558	0	0
check_trigger_regwen_rd_A	441261928	3214	0	0
consistency_check_period_rd_A	441261928	3472	0	0
creator_sw_cfg_read_lock_rd_A	441261928	2686	0	0
direct_access_address_rd_A	441261928	1894	0	0
direct_access_wdata_0_rd_A	441261928	1329	0	0
direct_access_wdata_1_rd_A	441261928	1435	0	0
integrity_check_period_rd_A	441261928	3183	0	0
intr_enable_rd_A	441261928	3942	0	0
owner_sw_cfg_read_lock_rd_A	441261928	2412	0	0
rot_creator_auth_codesign_read_lock_rd_A	441261928	2378	0	0
rot_creator_auth_state_read_lock_rd_A	441261928	2216	0	0
vendor_test_read_lock_rd_A	441261928	2470	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	7400755	0	0
T4	583932	174518	0	0
T5	56266	0	0	0
T6	123890	270228	0	0
T7	0	107376	0	0
T8	157366	0	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T13	0	101510	0	0
T14	0	148589	0	0
T15	0	73711	0	0
T22	15116	0	0	0
T67	13813	0	0	0
T105	12916	0	0	0
T154	0	65198	0	0
T162	0	75643	0	0
T163	0	142376	0	0
T295	0	167446	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	3091	0	0
T14	763082	115	0	0
T16	0	89	0	0
T18	0	60	0	0
T19	0	22	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	166	0	0
T276	0	103	0	0
T305	0	98	0	0
T379	0	136	0	0
T380	0	77	0	0
T381	0	69	0	0
T382	17367	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2558	0	0
T14	763082	249	0	0
T16	0	93	0	0
T18	0	40	0	0
T19	0	35	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	210	0	0
T276	0	92	0	0
T305	0	133	0	0
T379	0	195	0	0
T380	0	72	0	0
T381	0	72	0	0
T382	17367	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	3214	0	0
T14	763082	189	0	0
T16	0	80	0	0
T18	0	35	0	0
T19	0	37	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	161	0	0
T276	0	92	0	0
T305	0	134	0	0
T379	0	148	0	0
T380	0	58	0	0
T381	0	46	0	0
T382	17367	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	3472	0	0
T14	763082	226	0	0
T16	0	84	0	0
T18	0	38	0	0
T19	0	23	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	150	0	0
T276	0	102	0	0
T305	0	117	0	0
T379	0	229	0	0
T380	0	79	0	0
T381	0	52	0	0
T382	17367	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2686	0	0
T14	763082	178	0	0
T16	0	102	0	0
T18	0	55	0	0
T19	0	42	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	228	0	0
T276	0	93	0	0
T305	0	168	0	0
T379	0	165	0	0
T380	0	65	0	0
T381	0	59	0	0
T382	17367	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	1894	0	0
T14	763082	222	0	0
T16	0	82	0	0
T18	0	48	0	0
T19	0	32	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	187	0	0
T276	0	67	0	0
T305	0	156	0	0
T379	0	148	0	0
T380	0	95	0	0
T381	0	41	0	0
T382	17367	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	1329	0	0
T14	763082	147	0	0
T16	0	72	0	0
T18	0	22	0	0
T19	0	17	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	132	0	0
T276	0	26	0	0
T305	0	109	0	0
T379	0	172	0	0
T380	0	70	0	0
T381	0	37	0	0
T382	17367	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	1435	0	0
T14	763082	126	0	0
T16	0	57	0	0
T18	0	27	0	0
T19	0	7	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	152	0	0
T276	0	95	0	0
T305	0	82	0	0
T379	0	165	0	0
T380	0	49	0	0
T381	0	47	0	0
T382	17367	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	3183	0	0
T14	763082	133	0	0
T16	0	103	0	0
T18	0	37	0	0
T19	0	20	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	224	0	0
T276	0	103	0	0
T305	0	122	0	0
T379	0	184	0	0
T380	0	72	0	0
T381	0	26	0	0
T382	17367	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	3942	0	0
T14	763082	223	0	0
T16	0	134	0	0
T18	0	78	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T143	0	14	0	0
T163	0	123	0	0
T216	0	22	0	0
T379	0	141	0	0
T380	0	74	0	0
T381	0	92	0	0
T382	17367	0	0	0
T383	0	21	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2412	0	0
T14	763082	186	0	0
T16	0	67	0	0
T18	0	40	0	0
T19	0	27	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	215	0	0
T276	0	70	0	0
T305	0	116	0	0
T379	0	180	0	0
T380	0	87	0	0
T381	0	91	0	0
T382	17367	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2378	0	0
T14	763082	127	0	0
T16	0	55	0	0
T18	0	45	0	0
T19	0	28	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	192	0	0
T276	0	98	0	0
T305	0	110	0	0
T379	0	204	0	0
T380	0	56	0	0
T381	0	62	0	0
T382	17367	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2216	0	0
T14	763082	102	0	0
T16	0	71	0	0
T18	0	14	0	0
T19	0	10	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	187	0	0
T276	0	81	0	0
T305	0	141	0	0
T379	0	158	0	0
T380	0	51	0	0
T381	0	75	0	0
T382	17367	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441261928	2470	0	0
T14	763082	176	0	0
T16	0	83	0	0
T18	0	49	0	0
T19	0	26	0	0
T51	12079	0	0	0
T69	625613	0	0	0
T96	49462	0	0	0
T97	64655	0	0	0
T98	38215	0	0	0
T99	217604	0	0	0
T102	79118	0	0	0
T103	46498	0	0	0
T163	0	144	0	0
T276	0	80	0	0
T305	0	107	0	0
T379	0	194	0	0
T380	0	55	0	0
T381	0	40	0	0
T382	17367	0	0	0