Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
437896586 |
511100 |
0 |
0 |
T3 |
934593 |
27 |
0 |
0 |
T4 |
583932 |
1030 |
0 |
0 |
T5 |
56266 |
440 |
0 |
0 |
T6 |
123890 |
1284 |
0 |
0 |
T7 |
0 |
796 |
0 |
0 |
T8 |
157366 |
752 |
0 |
0 |
T9 |
12460 |
0 |
0 |
0 |
T10 |
127975 |
66 |
0 |
0 |
T11 |
9286 |
0 |
0 |
0 |
T25 |
0 |
746 |
0 |
0 |
T40 |
0 |
184 |
0 |
0 |
T67 |
13813 |
0 |
0 |
0 |
T105 |
12916 |
0 |
0 |
0 |
T108 |
0 |
832 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
437896586 |
511032 |
0 |
0 |
T3 |
934593 |
25 |
0 |
0 |
T4 |
583932 |
1030 |
0 |
0 |
T5 |
56266 |
440 |
0 |
0 |
T6 |
123890 |
1284 |
0 |
0 |
T7 |
0 |
796 |
0 |
0 |
T8 |
157366 |
752 |
0 |
0 |
T9 |
12460 |
0 |
0 |
0 |
T10 |
127975 |
66 |
0 |
0 |
T11 |
9286 |
0 |
0 |
0 |
T25 |
0 |
746 |
0 |
0 |
T40 |
0 |
184 |
0 |
0 |
T67 |
13813 |
0 |
0 |
0 |
T105 |
12916 |
0 |
0 |
0 |
T108 |
0 |
832 |
0 |
0 |