Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.75	95.45	92.86		91.67	90.91	82.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.40	96.65	92.86	100.00	91.67	92.54	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	100.00	100.00		100.00		100.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		132	126	95.45
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
ALWAYS	206	112	106	94.64
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
ALWAYS	750	3	3	100.00
ALWAYS	753	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
193	1	1
206	1	1
209	1	1
212	1	1
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
224	1	1
225	1	1
226	1	1
229	1	1
230	1	1
233	1	1
234	1	1
237	1	1
238	1	1
240	1	1
245	1	1
246	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
265	1	1
266	1	1
267	1	1
271	1	1
272	1	1
275	1	1
276		unreachable
278	1	1
279	1	1
282	1	1
283	1	1
			MISSING_ELSE
286	1	1
287	1	1
			MISSING_ELSE
298		excluded
			Exclude Annotation: VC_COV_UNR
299		excluded
			Exclude Annotation: VC_COV_UNR
300		excluded
			Exclude Annotation: VC_COV_UNR
301		excluded
			Exclude Annotation: VC_COV_UNR
302		excluded
			Exclude Annotation: VC_COV_UNR
303		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
311		excluded
			Exclude Annotation: VC_COV_UNR
312		excluded
			Exclude Annotation: VC_COV_UNR
313		excluded
			Exclude Annotation: VC_COV_UNR
314		excluded
			Exclude Annotation: VC_COV_UNR
315		excluded
			Exclude Annotation: VC_COV_UNR
316		excluded
			Exclude Annotation: VC_COV_UNR
317		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
324	1	1
325	1	1
326	1	1
331		unreachable
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
343	1	1
348	1	1
349	1	1
			==> MISSING_ELSE
351	1	1
352	1	1
			MISSING_ELSE
362	1	1
363	1	1
366	1	1
368	1	1
369	1	1
370	1	1
373	0	1
374	0	1
376	0	1
381		unreachable
385		unreachable
386		unreachable
387		unreachable
390		unreachable
391		unreachable
394		unreachable
395		unreachable
397		unreachable
401	1	1
402	1	1
			MISSING_ELSE
405	1	1
406	1	1
408	1	1
			MISSING_ELSE
417	1	1
418	1	1
419	1	1
420	1	1
423	1	1
424	1	1
425		unreachable
426		unreachable
427		unreachable
			==> MISSING_ELSE
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
443		unreachable
444		unreachable
445		unreachable
			==> MISSING_ELSE
455		excluded
			Exclude Annotation: VC_COV_UNR
456		excluded
			Exclude Annotation: VC_COV_UNR
457		excluded
			Exclude Annotation: VC_COV_UNR
458		excluded
			Exclude Annotation: VC_COV_UNR
459		excluded
			Exclude Annotation: VC_COV_UNR
460		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
467		excluded
			Exclude Annotation: VC_COV_UNR
468		excluded
			Exclude Annotation: VC_COV_UNR
469		excluded
			Exclude Annotation: VC_COV_UNR
470		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
480	1	1
481	1	1
482	1	1
483	1	1
485	1	1
489	1	1
490		excluded
			Exclude Annotation: VC_COV_UNR
491		excluded
			Exclude Annotation: VC_COV_UNR
493	1	1
494	1	1
498	0	1
499	0	1
			==> MISSING_ELSE
503	0	1
504		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
			==> MISSING_ELSE
528	1	1
529	1	1
530	1	1
531	1	1
532	1	1
			MISSING_ELSE
542	1	1
543	1	1
544	1	1
547	1	1
548	1	1
551	1	1
552	1	1
556	1	1
560	1	1
561	1	1
563	1	1
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
578	1	1
579	1	1
595	1	1
596		excluded
			Exclude Annotation: VC_COV_UNR
597		excluded
			Exclude Annotation: VC_COV_UNR
598		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
			MISSING_ELSE
			MISSING_ELSE
636	1	1
641	1	1
642	1	1
646	1	1
652	1	1
675	1	1
678	1	1
680	1	1
709	1	1
743	1	1
750	3	3
753	1	1
754	1	1
756	1	1
758	1	1
759	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	42	39	92.86
Logical	42	39	92.86
Non-Logical	0	0
Event	0	0

 LINE       271
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T24,T42

 LINE       302
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       368
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T6,T7
1	0	Covered	T8,T25,T12

 LINE       368
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T8,T10

 LINE       368
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T8,T25,T12
1	Covered	T4,T10,T6

 LINE       385
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       401
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T8,T10
1	Covered	T43,T44,T45

 LINE       426
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       433
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       485
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T46,T47,T48
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10

 LINE       547
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       547
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T1,T2,T3

 LINE       573
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T21

 LINE       597
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       605
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       636
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011000000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       636
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       709
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T8

 LINE       709
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	19	18	94.74
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests	Exclude Annotation
CnstyReadSt	334	Covered	T4,T8,T10
CnstyReadWaitSt	352	Covered	T4,T8,T10
ErrorSt	286	Covered	T1,T2,T3
IdleSt	369	Covered	T1,T2,T3
InitDescrSt	276	Excluded		VC_COV_UNR
InitDescrWaitSt	303	Excluded		VC_COV_UNR
InitSt	246	Covered	T1,T2,T3
InitWaitSt	256	Covered	T1,T2,T3
IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigFinSt	491	Covered	T1,T2,T3
IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt	434	Covered	T1,T2,T3
IntegDigWaitSt	532	Covered	T1,T2,T3
IntegScrSt	427	Excluded		VC_COV_UNR
IntegScrWaitSt	460	Excluded		VC_COV_UNR
ResetSt	244	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
CnstyReadSt->CnstyReadWaitSt	352	Covered	T4,T8,T10
CnstyReadSt->ErrorSt	596	Covered	T4,T12,T50
CnstyReadWaitSt->CnstyReadSt	390	Excluded		VC_COV_UNR
CnstyReadWaitSt->ErrorSt	373	Covered	T43,T82,T83
CnstyReadWaitSt->IdleSt	369	Covered	T4,T8,T10
IdleSt->CnstyReadSt	334	Covered	T4,T8,T10
IdleSt->ErrorSt	596	Covered	T3,T4,T5
IdleSt->IntegDigClrSt	326	Covered	T4,T5,T8
InitDescrSt->ErrorSt	596	Excluded
InitDescrSt->InitDescrWaitSt	303	Excluded
InitDescrWaitSt->ErrorSt	596	Excluded
InitDescrWaitSt->InitSt	315	Excluded
InitSt->ErrorSt	596	Covered	T1,T67,T31
InitSt->InitWaitSt	256	Covered	T1,T2,T3
InitWaitSt->ErrorSt	286	Covered	T2,T80,T81
InitWaitSt->InitDescrSt	276	Excluded
InitWaitSt->InitSt	278	Excluded	T1,T2,T3
InitWaitSt->IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigClrSt->ErrorSt	596	Covered	T7,T68,T69
IntegDigClrSt->IdleSt	443	Excluded		VC_COV_UNR
IntegDigClrSt->IntegDigSt	434	Excluded	T1,T2,T3
IntegDigClrSt->IntegScrSt	427	Excluded
IntegDigFinSt->ErrorSt	596	Covered	T59,T70,T71
IntegDigFinSt->IntegDigWaitSt	532	Covered	T1,T2,T3
IntegDigPadSt->ErrorSt	596	Excluded
IntegDigPadSt->IntegDigFinSt	520	Excluded	T1,T2,T3
IntegDigSt->ErrorSt	596	Not Covered
IntegDigSt->IntegDigFinSt	491	Excluded		VC_COV_UNR
IntegDigSt->IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt->IntegScrSt	504	Excluded
IntegDigWaitSt->ErrorSt	560	Covered	T46,T47,T48
IntegDigWaitSt->IdleSt	548	Covered	T1,T2,T3
IntegScrSt->ErrorSt	596	Excluded
IntegScrSt->IntegScrWaitSt	460	Excluded
IntegScrWaitSt->ErrorSt	596	Excluded
IntegScrWaitSt->IntegDigSt	470	Excluded
ResetSt->ErrorSt	596	Covered	T75,T76,T77
ResetSt->InitSt	246	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	374	Covered	T46,T47,T48
FsmStateError	574	Covered	T1,T3,T4
MacroEccCorrError	283	Covered	T43,T41,T24
NoError	573	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
CheckFailError->FsmStateError	606	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	283	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	374	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	283	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	374	Not Covered
MacroEccCorrError->FsmStateError	606	Covered	T41,T24,T42
NoError->CheckFailError	374	Covered	T46,T47,T48
NoError->FsmStateError	574	Covered	T1,T3,T4
NoError->MacroEccCorrError	283	Covered	T43,T41,T24

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		55	50	90.91
TERNARY	636	2	2	100.00
TERNARY	652	2	2	100.00
TERNARY	678	2	2	100.00
TERNARY	709	2	2	100.00
CASE	240	39	34	87.18
IF	595	1	1	100.00
IF	602	3	3	100.00
IF	750	2	2	100.00
IF	753	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	636	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	678	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	709	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	case (state_q)
-2-:	245	if (init_req_i)
-3-:	255	if (otp_gnt_i)
-4-:	265	if (otp_rvalid_i)
-5-:	267	if ((otp_err inside {NoError, MacroEccCorrError}))
-6-:	271	if ((cnt == LastScrmblBlock))
-7-:	275	if (1'b0)
-8-:	282	if ((otp_err != NoError))
-9-:	302	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	314	if (scrmbl_valid_i)
-11-:	324	if (integ_chk_req_i)
-12-:	325	if (1'b1)
-13-:	333	if (cnsty_chk_req_i)
-14-:	348	if (1'b1)
-15-:	351	if (otp_gnt_i)
-16-:	362	if (otp_rvalid_i)
-17-:	363	if ((otp_err inside {NoError, MacroEccCorrError}))
-18-:	366	if (1'b1)
-19-:	368	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	381	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	385	if ((cnt == LastScrmblBlock))
-22-:	401	if ((otp_err != NoError))
-23-:	417	if (1'b1)
-24-:	424	if (1'b0)
-25-:	426	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	433	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	444	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	459	if (scrmbl_ready_i)
-29-:	469	if (scrmbl_valid_i)
-30-:	482	if (scrmbl_ready_i)
-31-:	485	if ((cnt == PenultimateScrmblBlock))
-32-:	489	if (cnt[0])
-33-:	498	if (cnt[0])
-34-:	503	if (1'b0)
-35-:	519	if (scrmbl_ready_i)
-36-:	531	if (scrmbl_ready_i)
-37-:	544	if (scrmbl_valid_i)
-38-:	547	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	551	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	573	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests	Exclude Annotation
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T24,T42
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T80,T81
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T43,T44,T45
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T82,T26,T117
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T10
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T4,T5,T8
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T46,T47,T48
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	595	if (ecc_err)
-2-:	597	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	605	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	753	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	34	97.14	29	82.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	34	97.14	29	82.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	437896586	437028507	0	0
BypassEnable0_A	437896586	0	0	0
BypassEnable1_A	437896586	437028507	0	0
CnstyChkAckKnown_A	437896586	437028507	0	0
DataKnown_A	437896586	437028507	0	0
DigestKnown_A	437896586	437028507	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	437896586	0	0	0
ErrorKnown_A	437896586	437028507	0	0
InitDoneKnown_A	437896586	437028507	0	0
InitReadLocksPartition_A	437896586	82298324	0	0
InitWriteLocksPartition_A	437896586	82298324	0	0
IntegChkAckKnown_A	437896586	437028507	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	437896586	437028507	0	0
OtpCmdKnown_A	437896586	437028507	0	0
OtpErrorState_A	0	0	0	0
OtpPartBufSize_A	1145	1145	0	0
OtpReqKnown_A	437896586	437028507	0	0
OtpSizeKnown_A	437896586	437028507	0	0
OtpWdataKnown_A	437896586	437028507	0	0
ReadLockImpliesDigest_A	437896586	437028507	0	0
ReadLockPropagation_A	437896586	0	0	0
ScrambledImpliesDigest_A	437896586	0	0	0
ScrmblCmdKnown_A	437896586	437028507	0	0
ScrmblDataKnown_A	435746818	434922203	0	0
ScrmblModeKnown_A	437896586	437028507	0	0
ScrmblMtxReqKnown_A	437896586	437028507	0	0
ScrmblSelKnown_A	437896586	437028507	0	0
ScrmblValidKnown_A	437896586	437028507	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
WriteLockImpliesDigest_A	437896586	0	0	0
WriteLockPropagation_A	437896586	2195104	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	437896586	25605579	0	0
u_state_regs_A	437896586	437028507	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	0	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	82298324	0	0
T1	13729	4746	0	0
T2	11237	5355	0	0
T3	934593	168462	0	0
T4	583932	931573	0	0
T5	56266	12580	0	0
T6	123890	533899	0	0
T8	157366	7301	0	0
T9	12460	1689	0	0
T10	127975	2620	0	0
T11	9286	3989	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	82298324	0	0
T1	13729	4746	0	0
T2	11237	5355	0	0
T3	934593	168462	0	0
T4	583932	931573	0	0
T5	56266	12580	0	0
T6	123890	533899	0	0
T8	157366	7301	0	0
T9	12460	1689	0	0
T10	127975	2620	0	0
T11	9286	3989	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpPartBufSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	0	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	0	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435746818	434922203	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	577192	563607	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	0	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	2195104	0	0
T12	296450	6912	0	0
T13	464558	0	0	0
T50	0	4726	0	0
T69	0	20938	0	0
T93	0	7265	0	0
T98	0	1288	0	0
T100	153440	9094	0	0
T101	76357	0	0	0
T102	0	3515	0	0
T103	0	1521	0	0
T104	0	10124	0	0
T111	35369	0	0	0
T118	0	4008	0	0
T119	14059	0	0	0
T120	27619	0	0	0
T121	8534	0	0	0
T122	10769	0	0	0
T123	15500	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	25605579	0	0
T2	11237	3984	0	0
T3	934593	0	0	0
T4	583932	0	0	0
T5	56266	2431	0	0
T6	123890	0	0	0
T8	157366	136363	0	0
T9	12460	0	0	0
T10	127975	3065	0	0
T11	9286	0	0	0
T12	0	112587	0	0
T25	0	40060	0	0
T28	0	4255	0	0
T31	0	2491	0	0
T40	0	5205	0	0
T105	12916	0	0	0
T111	0	11324	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0