Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T79,T168

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T108,T50

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T169,T170
1	Covered	T169,T170

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T31,T121,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T173,T196
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T8
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T176,T225,T226
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T5,T8
CheckFailError	317	Covered	T169,T170
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T10,T67,T108
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T108,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T169,T170
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T67,T108,T79
MacroEccCorrError->NoError	235	Covered	T10,T50,T43
NoError->AccessError	256	Covered	T4,T5,T8
NoError->CheckFailError	317	Covered	T169,T170
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T10,T67,T108

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T67,T79,T168
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T173,T227
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T25,T12
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T10,T108,T50
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T176,T225,T226
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T169,T170
1	0	Covered	T169,T170
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	437896586	437028507	0	0
DigestKnown_A	437896586	437028507	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	437896586	6686	0	0
ErrorKnown_A	437896586	437028507	0	0
FsmStateKnown_A	437896586	437028507	0	0
InitDoneKnown_A	437896586	437028507	0	0
InitReadLocksPartition_A	437896586	79872201	0	0
InitWriteLocksPartition_A	437896586	79872201	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	437896586	437028507	0	0
OtpCmdKnown_A	437896586	437028507	0	0
OtpErrorState_A	437896586	34	0	0
OtpReqKnown_A	437896586	437028507	0	0
OtpSizeKnown_A	437896586	437028507	0	0
OtpWdataKnown_A	437896586	437028507	0	0
ReadLockPropagation_A	437896586	173607711	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	437896586	437028507	0	0
TlulRdataKnown_A	437896586	437028507	0	0
TlulReadOnReadLock_A	437896586	7676	0	0
TlulRerrorKnown_A	437896586	437028507	0	0
TlulRvalidKnown_A	437896586	437028507	0	0
WriteLockPropagation_A	437896586	2378985	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	437896586	26564787	0	0
u_state_regs_A	437896586	437028507	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	6686	0	0
T169	10453	3515	0	0
T170	0	3171	0	0
T228	63155	0	0	0
T229	12354	0	0	0
T230	32694	0	0	0
T231	11186	0	0	0
T232	214383	0	0	0
T233	40242	0	0	0
T234	13090	0	0	0
T235	23418	0	0	0
T236	19210	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	79872201	0	0
T1	13729	4278	0	0
T2	11237	4970	0	0
T3	934593	88968	0	0
T4	583932	930171	0	0
T5	56266	10243	0	0
T6	123890	532496	0	0
T8	157366	4128	0	0
T9	12460	987	0	0
T10	127975	2152	0	0
T11	9286	3288	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	79872201	0	0
T1	13729	4278	0	0
T2	11237	4970	0	0
T3	934593	88968	0	0
T4	583932	930171	0	0
T5	56266	10243	0	0
T6	123890	532496	0	0
T8	157366	4128	0	0
T9	12460	987	0	0
T10	127975	2152	0	0
T11	9286	3288	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	34	0	0
T1	13729	1	0	0
T2	11237	0	0	0
T3	934593	0	0	0
T4	583932	0	0	0
T5	56266	0	0	0
T6	123890	0	0	0
T8	157366	0	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T173	0	1	0	0
T176	0	1	0	0
T184	0	1	0	0
T227	0	1	0	0
T237	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	173607711	0	0
T4	583932	102471	0	0
T5	56266	9691	0	0
T6	123890	767990	0	0
T7	0	674033	0	0
T8	157366	48271	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T12	0	45295	0	0
T22	15116	0	0	0
T25	0	7716	0	0
T31	0	1606	0	0
T67	13813	0	0	0
T105	12916	0	0	0
T108	0	4715	0	0
T111	0	9739	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	7676	0	0
T3	934593	75	0	0
T4	583932	18	0	0
T5	56266	3	0	0
T6	123890	12	0	0
T7	0	25	0	0
T8	157366	14	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T25	0	12	0	0
T31	0	10	0	0
T67	13813	0	0	0
T105	12916	2	0	0
T108	0	18	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	2378985	0	0
T6	123890	0	0	0
T8	157366	20263	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T12	0	11414	0	0
T22	15116	0	0	0
T25	57700	3060	0	0
T40	16016	0	0	0
T67	13813	0	0	0
T93	0	3467	0	0
T95	0	741	0	0
T98	0	3784	0	0
T100	0	9503	0	0
T101	0	24531	0	0
T102	0	3628	0	0
T105	12916	0	0	0
T111	0	3515	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	26564787	0	0
T1	13729	3217	0	0
T2	11237	0	0	0
T3	934593	0	0	0
T4	583932	0	0	0
T5	56266	0	0	0
T6	123890	0	0	0
T8	157366	138330	0	0
T9	12460	0	0	0
T10	127975	3218	0	0
T11	9286	0	0	0
T12	0	149666	0	0
T25	0	50802	0	0
T31	0	2644	0	0
T100	0	137858	0	0
T108	0	4433	0	0
T111	0	25520	0	0
T119	0	4562	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T80,T81,T115

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T108,T50

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T159,T171,T174
1	Covered	T159,T171,T174

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T67,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T67,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T31,T121,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T67,T114
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T8,T6
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T242,T243,T244
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T8,T6
CheckFailError	317	Covered	T159,T171,T174
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T10,T108,T50
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T108,T12
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T8,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T159,T171,T174
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T108,T80,T81
MacroEccCorrError->NoError	235	Covered	T10,T50,T43
NoError->AccessError	256	Covered	T4,T8,T6
NoError->CheckFailError	317	Covered	T159,T171,T174
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T10,T108,T50

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T67,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T80,T81,T115
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T67,T114,T245
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T25,T7
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T8,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T10,T108,T50
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T242,T243,T244
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T159,T171,T174
1	0	Covered	T159,T171,T174
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	437896586	437028507	0	0
DigestKnown_A	437896586	437028507	0	0
DigestOffsetMustBeRepresentable_A	1145	1145	0	0
EccErrorState_A	437896586	20311	0	0
ErrorKnown_A	437896586	437028507	0	0
FsmStateKnown_A	437896586	437028507	0	0
InitDoneKnown_A	437896586	437028507	0	0
InitReadLocksPartition_A	437896586	80051070	0	0
InitWriteLocksPartition_A	437896586	80051070	0	0
OffsetMustBeBlockAligned_A	1145	1145	0	0
OtpAddrKnown_A	437896586	437028507	0	0
OtpCmdKnown_A	437896586	437028507	0	0
OtpErrorState_A	437896586	35	0	0
OtpReqKnown_A	437896586	437028507	0	0
OtpSizeKnown_A	437896586	437028507	0	0
OtpWdataKnown_A	437896586	437028507	0	0
ReadLockPropagation_A	437896586	159764909	0	0
SizeMustBeBlockAligned_A	1145	1145	0	0
TlulGntKnown_A	437896586	437028507	0	0
TlulRdataKnown_A	437896586	437028507	0	0
TlulReadOnReadLock_A	437896586	7526	0	0
TlulRerrorKnown_A	437896586	437028507	0	0
TlulRvalidKnown_A	437896586	437028507	0	0
WriteLockPropagation_A	437896586	930949	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	437896586	10349229	0	0
u_state_regs_A	437896586	437028507	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	20311	0	0
T26	91826	0	0	0
T159	11619	2732	0	0
T169	0	3515	0	0
T171	0	3658	0	0
T172	0	3023	0	0
T174	0	2344	0	0
T177	0	2542	0	0
T178	0	2497	0	0
T246	15604	0	0	0
T247	41887	0	0	0
T248	55100	0	0	0
T249	11891	0	0	0
T250	11766	0	0	0
T251	76727	0	0	0
T252	10287	0	0	0
T253	9511	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	80051070	0	0
T1	13729	4312	0	0
T2	11237	5004	0	0
T3	934593	94765	0	0
T4	583932	930273	0	0
T5	56266	10413	0	0
T6	123890	532598	0	0
T8	157366	4366	0	0
T9	12460	1038	0	0
T10	127975	2186	0	0
T11	9286	3339	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	80051070	0	0
T1	13729	4312	0	0
T2	11237	5004	0	0
T3	934593	94765	0	0
T4	583932	930273	0	0
T5	56266	10413	0	0
T6	123890	532598	0	0
T8	157366	4366	0	0
T9	12460	1038	0	0
T10	127975	2186	0	0
T11	9286	3339	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	35	0	0
T7	722142	0	0	0
T22	15116	0	0	0
T25	57700	0	0	0
T28	15656	0	0	0
T31	13215	0	0	0
T40	16016	0	0	0
T67	13813	1	0	0
T107	20406	0	0	0
T108	95465	0	0	0
T109	64294	0	0	0
T114	0	1	0	0
T168	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T254	0	1	0	0
T255	0	1	0	0
T256	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	159764909	0	0
T4	583932	102459	0	0
T5	56266	0	0	0
T6	123890	752106	0	0
T7	0	674151	0	0
T8	157366	54091	0	0
T9	12460	0	0	0
T10	127975	512	0	0
T11	9286	0	0	0
T12	0	40304	0	0
T22	15116	0	0	0
T25	0	7309	0	0
T67	13813	0	0	0
T105	12916	0	0	0
T107	0	6623	0	0
T108	0	5663	0	0
T110	0	56388	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1145	1145	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	7526	0	0
T3	934593	4	0	0
T4	583932	16	0	0
T5	56266	2	0	0
T6	123890	6	0	0
T7	0	19	0	0
T8	157366	11	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	4	0	0
T25	0	8	0	0
T31	0	6	0	0
T67	13813	0	0	0
T105	12916	0	0	0
T108	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	930949	0	0
T6	123890	0	0	0
T8	157366	25157	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T12	0	4448	0	0
T22	15116	0	0	0
T25	57700	0	0	0
T40	16016	0	0	0
T67	13813	0	0	0
T69	0	8873	0	0
T95	0	599	0	0
T98	0	8584	0	0
T104	0	17888	0	0
T105	12916	0	0	0
T215	0	6095	0	0
T216	0	29892	0	0
T217	0	29811	0	0
T218	0	320	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	10349229	0	0
T6	123890	0	0	0
T8	157366	138109	0	0
T9	12460	0	0	0
T10	127975	0	0	0
T11	9286	0	0	0
T12	0	79857	0	0
T22	15116	0	0	0
T25	57700	0	0	0
T40	16016	0	0	0
T67	13813	2175	0	0
T69	0	148751	0	0
T95	0	58033	0	0
T98	0	29305	0	0
T103	0	27981	0	0
T104	0	144486	0	0
T105	12916	0	0	0
T114	0	2705	0	0
T212	0	2576	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437896586	437028507	0	0
T1	13729	13468	0	0
T2	11237	11006	0	0
T3	934593	912373	0	0
T4	583932	583922	0	0
T5	56266	55350	0	0
T6	123890	123889	0	0
T8	157366	156124	0	0
T9	12460	11165	0	0
T10	127975	127705	0	0
T11	9286	9022	0	0