Module Definition
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Module Instance : tb.dut.u_otp_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.68 100.00 94.74 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.83 100.00 92.31 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.19 94.16 96.15 97.02 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 95.00 89.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T5,T8
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.68 94.74
tb.dut.u_otp_rsp_fifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

SCOREBRANCH
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 253457731 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1751586344 37913142 0 0
gen_passthru_fifo.paramCheckPass 7920 7920 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 253457731 0 0
T1 137290 6075 0 0
T2 112370 8647 0 0
T3 9345930 371368 0 0
T4 5839320 2527400 0 0
T5 562660 26002 0 0
T6 1238900 3678981 0 0
T8 1573660 74025 0 0
T9 124600 10321 0 0
T10 1279750 6687 0 0
T11 92860 3873 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 137290 134680 0 0
T2 112370 110060 0 0
T3 9345930 9123730 0 0
T4 5839320 5839220 0 0
T5 562660 553500 0 0
T6 1238900 1238890 0 0
T8 1573660 1561240 0 0
T9 124600 111650 0 0
T10 1279750 1277050 0 0
T11 92860 90220 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 137290 134680 0 0
T2 112370 110060 0 0
T3 9345930 9123730 0 0
T4 5839320 5839220 0 0
T5 562660 553500 0 0
T6 1238900 1238890 0 0
T8 1573660 1561240 0 0
T9 124600 111650 0 0
T10 1279750 1277050 0 0
T11 92860 90220 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 137290 134680 0 0
T2 112370 110060 0 0
T3 9345930 9123730 0 0
T4 5839320 5839220 0 0
T5 562660 553500 0 0
T6 1238900 1238890 0 0
T8 1573660 1561240 0 0
T9 124600 111650 0 0
T10 1279750 1277050 0 0
T11 92860 90220 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1751586344 37913142 0 0
T1 54916 3433 0 0
T2 44948 3247 0 0
T3 3738372 319956 0 0
T4 2335728 280747 0 0
T5 225064 10880 0 0
T6 495560 515220 0 0
T8 629464 22735 0 0
T9 49840 3349 0 0
T10 511900 3019 0 0
T11 37144 2613 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 7920 7920 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 437896586 17060266 0 0
DepthKnown_A 437896586 437028507 0 0
RvalidKnown_A 437896586 437028507 0 0
WreadyKnown_A 437896586 437028507 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 437896586 17060266 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 17060266 0 0
T1 13729 2971 0 0
T2 11237 2638 0 0
T3 934593 319176 0 0
T4 583932 16792 0 0
T5 56266 10724 0 0
T6 123890 87439 0 0
T8 157366 21684 0 0
T9 12460 3286 0 0
T10 127975 2878 0 0
T11 9286 2583 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 17060266 0 0
T1 13729 2971 0 0
T2 11237 2638 0 0
T3 934593 319176 0 0
T4 583932 16792 0 0
T5 56266 10724 0 0
T6 123890 87439 0 0
T8 157366 21684 0 0
T9 12460 3286 0 0
T10 127975 2878 0 0
T11 9286 2583 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 58603544 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 58603544 0 0
T1 13729 629 0 0
T2 11237 1350 0 0
T3 934593 12853 0 0
T4 583932 126230 0 0
T5 56266 1814 0 0
T6 123890 134892 0 0
T8 157366 12763 0 0
T9 12460 1743 0 0
T10 127975 908 0 0
T11 9286 315 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 53743107 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 53743107 0 0
T1 13729 692 0 0
T2 11237 1350 0 0
T3 934593 12853 0 0
T4 583932 561348 0 0
T5 56266 5747 0 0
T6 123890 858794 0 0
T8 157366 12882 0 0
T9 12460 1743 0 0
T10 127975 926 0 0
T11 9286 315 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 24743717 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 24743717 0 0
T1 13729 16 0 0
T2 11237 29 0 0
T3 934593 260 0 0
T4 583932 558310 0 0
T5 56266 12 0 0
T6 123890 850559 0 0
T8 157366 91 0 0
T9 12460 3 0 0
T10 127975 5 0 0
T11 9286 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 19330006 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 19330006 0 0
T1 13729 79 0 0
T2 11237 29 0 0
T3 934593 260 0 0
T4 583932 263733 0 0
T5 56266 54 0 0
T6 123890 417927 0 0
T8 157366 210 0 0
T9 12460 3 0 0
T10 127975 23 0 0
T11 9286 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 24711114 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 24711114 0 0
T1 13729 613 0 0
T2 11237 1321 0 0
T3 934593 12593 0 0
T4 583932 439417 0 0
T5 56266 1802 0 0
T6 123890 460722 0 0
T8 157366 12672 0 0
T9 12460 1740 0 0
T10 127975 903 0 0
T11 9286 305 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 441261928 34413101 0 0
DepthKnown_A 441261928 440336945 0 0
RvalidKnown_A 441261928 440336945 0 0
WreadyKnown_A 441261928 440336945 0 0
gen_passthru_fifo.paramCheckPass 1320 1320 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 34413101 0 0
T1 13729 613 0 0
T2 11237 1321 0 0
T3 934593 12593 0 0
T4 583932 297615 0 0
T5 56266 5693 0 0
T6 123890 440867 0 0
T8 157366 12672 0 0
T9 12460 1740 0 0
T10 127975 903 0 0
T11 9286 305 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441261928 440336945 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1320 1320 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T4
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 437896586 19898162 0 0
DepthKnown_A 437896586 437028507 0 0
RvalidKnown_A 437896586 437028507 0 0
WreadyKnown_A 437896586 437028507 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 437896586 19898162 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 19898162 0 0
T1 13729 223 0 0
T2 11237 290 0 0
T3 934593 260 0 0
T4 583932 263778 0 0
T5 56266 72 0 0
T6 123890 421747 0 0
T8 157366 480 0 0
T9 12460 30 0 0
T10 127975 68 0 0
T11 9286 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 19898162 0 0
T1 13729 223 0 0
T2 11237 290 0 0
T3 934593 260 0 0
T4 583932 263778 0 0
T5 56266 72 0 0
T6 123890 421747 0 0
T8 157366 480 0 0
T9 12460 30 0 0
T10 127975 68 0 0
T11 9286 10 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T4
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 437896586 696275 0 0
DepthKnown_A 437896586 437028507 0 0
RvalidKnown_A 437896586 437028507 0 0
WreadyKnown_A 437896586 437028507 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 437896586 696275 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 696275 0 0
T1 13729 160 0 0
T2 11237 290 0 0
T3 934593 260 0 0
T4 583932 111 0 0
T5 56266 30 0 0
T6 123890 4295 0 0
T8 157366 361 0 0
T9 12460 30 0 0
T10 127975 50 0 0
T11 9286 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 696275 0 0
T1 13729 160 0 0
T2 11237 290 0 0
T3 934593 260 0 0
T4 583932 111 0 0
T5 56266 30 0 0
T6 123890 4295 0 0
T8 157366 361 0 0
T9 12460 30 0 0
T10 127975 50 0 0
T11 9286 10 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T5,T8
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 437896586 258439 0 0
DepthKnown_A 437896586 437028507 0 0
RvalidKnown_A 437896586 437028507 0 0
WreadyKnown_A 437896586 437028507 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 437896586 258439 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 258439 0 0
T1 13729 79 0 0
T2 11237 29 0 0
T3 934593 260 0 0
T4 583932 66 0 0
T5 56266 54 0 0
T6 123890 1739 0 0
T8 157366 210 0 0
T9 12460 3 0 0
T10 127975 23 0 0
T11 9286 10 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 437028507 0 0
T1 13729 13468 0 0
T2 11237 11006 0 0
T3 934593 912373 0 0
T4 583932 583922 0 0
T5 56266 55350 0 0
T6 123890 123889 0 0
T8 157366 156124 0 0
T9 12460 11165 0 0
T10 127975 127705 0 0
T11 9286 9022 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 437896586 258439 0 0
T1 13729 79 0 0
T2 11237 29 0 0
T3 934593 260 0 0
T4 583932 66 0 0
T5 56266 54 0 0
T6 123890 1739 0 0
T8 157366 210 0 0
T9 12460 3 0 0
T10 127975 23 0 0
T11 9286 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%