Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7116036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7025419

1

T1

357

T2

224

T3

305

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8215030	1			T1	2832		T2	821		T3	975
values[0x0]	2255396	1			T1	54		T2	123		T3	48
values[0x1]	3671029	1			T1	61		T2	127		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4617167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9524288

1

T1

1174

T2

481

T3

517

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63347	1			T1	9		T2	1		T3	1
valid_sources[0x01]	50663	1			T1	14		T3	3		T8	1
valid_sources[0x02]	55429	1			T1	15		T2	4		T3	3
valid_sources[0x03]	53072	1			T1	10		T2	2		T3	4
valid_sources[0x04]	53194	1			T1	17		T2	5		T3	2
valid_sources[0x05]	49250	1			T1	10		T2	2		T3	11
valid_sources[0x06]	60217	1			T1	9		T2	2		T3	1
valid_sources[0x07]	52760	1			T1	7		T2	3		T3	4
valid_sources[0x08]	58298	1			T1	21		T2	7		T8	4
valid_sources[0x09]	49156	1			T1	11		T2	2		T8	7
valid_sources[0x0a]	59095	1			T1	9		T2	1		T3	2
valid_sources[0x0b]	57915	1			T1	8		T2	3		T3	11
valid_sources[0x0c]	56134	1			T1	15		T2	5		T3	6
valid_sources[0x0d]	53108	1			T1	6		T2	5		T3	4
valid_sources[0x0e]	50119	1			T1	18		T2	3		T3	9
valid_sources[0x0f]	49193	1			T1	6		T2	5		T8	3
valid_sources[0x10]	56021	1			T1	12		T8	3		T9	5
valid_sources[0x11]	49655	1			T1	7		T2	1		T3	3
valid_sources[0x12]	55924	1			T1	9		T2	4		T9	4
valid_sources[0x13]	56714	1			T1	10		T2	11		T3	13
valid_sources[0x14]	57366	1			T1	10		T3	4		T8	1
valid_sources[0x15]	51364	1			T1	20		T2	4		T3	5
valid_sources[0x16]	50845	1			T1	10		T9	4		T10	2
valid_sources[0x17]	50044	1			T1	20		T2	6		T3	4
valid_sources[0x18]	52618	1			T1	14		T2	12		T3	29
valid_sources[0x19]	64155	1			T1	8		T2	3		T3	1
valid_sources[0x1a]	71639	1			T1	19		T2	9		T3	12
valid_sources[0x1b]	48722	1			T1	17		T2	5		T3	3
valid_sources[0x1c]	55757	1			T1	9		T2	2		T8	5
valid_sources[0x1d]	51997	1			T1	8		T2	7		T8	2
valid_sources[0x1e]	59238	1			T1	17		T2	2		T3	3
valid_sources[0x1f]	51168	1			T1	19		T2	1		T3	3
valid_sources[0x20]	51603	1			T1	20		T2	7		T9	1
valid_sources[0x21]	64218	1			T1	13		T2	11		T3	20
valid_sources[0x22]	54781	1			T1	7		T2	6		T3	3
valid_sources[0x23]	52774	1			T1	9		T2	4		T8	1
valid_sources[0x24]	50216	1			T1	12		T2	7		T3	9
valid_sources[0x25]	50528	1			T1	15		T2	9		T3	6
valid_sources[0x26]	50343	1			T1	10		T3	7		T8	7
valid_sources[0x27]	48380	1			T1	9		T2	2		T8	6
valid_sources[0x28]	52832	1			T1	9		T2	1		T9	3
valid_sources[0x29]	54242	1			T1	20		T2	4		T3	8
valid_sources[0x2a]	61472	1			T1	6		T2	1		T8	1
valid_sources[0x2b]	49400	1			T1	9		T2	2		T9	17
valid_sources[0x2c]	52198	1			T1	12		T2	3		T8	16
valid_sources[0x2d]	55584	1			T1	9		T2	5		T8	7
valid_sources[0x2e]	50290	1			T1	9		T2	6		T3	1
valid_sources[0x2f]	48458	1			T1	11		T2	4		T9	10
valid_sources[0x30]	54682	1			T1	16		T9	8		T10	4
valid_sources[0x31]	64303	1			T1	16		T2	9		T8	3
valid_sources[0x32]	49007	1			T1	11		T2	3		T8	12
valid_sources[0x33]	116732	1			T1	4		T2	6		T3	8
valid_sources[0x34]	50139	1			T1	11		T2	4		T3	3
valid_sources[0x35]	48573	1			T1	6		T2	15		T8	3
valid_sources[0x36]	50409	1			T1	12		T2	6		T3	2
valid_sources[0x37]	48184	1			T1	9		T8	12		T9	5
valid_sources[0x38]	63974	1			T1	12		T2	2		T8	6
valid_sources[0x39]	51823	1			T1	21		T2	2		T3	8
valid_sources[0x3a]	50528	1			T1	8		T2	3		T3	5
valid_sources[0x3b]	50122	1			T1	16		T2	6		T8	3
valid_sources[0x3c]	49121	1			T1	19		T2	1		T9	6
valid_sources[0x3d]	49997	1			T1	7		T2	11		T3	15
valid_sources[0x3e]	58746	1			T1	11		T2	4		T3	8
valid_sources[0x3f]	52683	1			T1	11		T2	1		T3	7
valid_sources[0x40]	51625	1			T1	9		T2	2		T3	9
valid_sources[0x41]	56612	1			T1	19		T2	2		T3	13
valid_sources[0x42]	51387	1			T1	8		T2	5		T3	9
valid_sources[0x43]	53045	1			T1	10		T2	7		T3	7
valid_sources[0x44]	58499	1			T1	11		T2	16		T8	7
valid_sources[0x45]	54462	1			T1	13		T2	2		T3	14
valid_sources[0x46]	50876	1			T1	7		T2	7		T3	2
valid_sources[0x47]	51787	1			T1	12		T3	3		T8	4
valid_sources[0x48]	53014	1			T1	12		T2	7		T3	3
valid_sources[0x49]	52941	1			T1	13		T2	10		T3	9
valid_sources[0x4a]	49587	1			T1	12		T2	4		T3	5
valid_sources[0x4b]	87461	1			T1	12		T2	2		T3	8
valid_sources[0x4c]	48927	1			T1	11		T2	12		T3	3
valid_sources[0x4d]	55981	1			T1	12		T2	2		T3	1
valid_sources[0x4e]	50461	1			T1	11		T2	2		T8	7
valid_sources[0x4f]	53036	1			T1	13		T2	3		T3	7
valid_sources[0x50]	67927	1			T1	16		T2	1		T3	2
valid_sources[0x51]	52590	1			T1	8		T2	4		T9	5
valid_sources[0x52]	54377	1			T1	13		T2	6		T3	1
valid_sources[0x53]	49251	1			T1	17		T2	3		T8	2
valid_sources[0x54]	64627	1			T1	20		T3	2		T8	5
valid_sources[0x55]	50166	1			T1	10		T2	3		T3	11
valid_sources[0x56]	50981	1			T1	8		T2	3		T3	3
valid_sources[0x57]	52868	1			T1	10		T2	9		T3	13
valid_sources[0x58]	56055	1			T1	15		T2	13		T3	7
valid_sources[0x59]	53438	1			T1	8		T2	7		T8	7
valid_sources[0x5a]	52021	1			T1	10		T2	3		T3	2
valid_sources[0x5b]	48097	1			T1	3		T2	2		T9	11
valid_sources[0x5c]	56215	1			T1	11		T2	2		T8	3
valid_sources[0x5d]	61037	1			T1	10		T3	12		T8	10
valid_sources[0x5e]	49323	1			T1	17		T2	2		T8	7
valid_sources[0x5f]	58542	1			T1	22		T2	4		T3	12
valid_sources[0x60]	51738	1			T1	7		T2	2		T3	4
valid_sources[0x61]	48427	1			T1	14		T2	12		T3	11
valid_sources[0x62]	50263	1			T1	19		T2	4		T3	5
valid_sources[0x63]	52384	1			T1	19		T2	3		T3	2
valid_sources[0x64]	48144	1			T1	7		T3	5		T8	4
valid_sources[0x65]	50994	1			T1	6		T3	6		T8	12
valid_sources[0x66]	49964	1			T1	12		T2	2		T8	7
valid_sources[0x67]	57580	1			T1	11		T2	2		T3	6
valid_sources[0x68]	54518	1			T1	12		T2	4		T9	4
valid_sources[0x69]	51235	1			T1	7		T2	2		T3	8
valid_sources[0x6a]	54412	1			T1	8		T2	3		T8	2
valid_sources[0x6b]	52343	1			T1	15		T2	1		T3	5
valid_sources[0x6c]	47950	1			T1	17		T2	2		T3	1
valid_sources[0x6d]	49435	1			T1	11		T3	4		T8	9
valid_sources[0x6e]	60411	1			T1	11		T3	3		T8	4
valid_sources[0x6f]	49903	1			T1	16		T3	5		T8	5
valid_sources[0x70]	49651	1			T1	8		T2	2		T3	2
valid_sources[0x71]	51070	1			T1	13		T2	3		T8	10
valid_sources[0x72]	51047	1			T1	12		T2	7		T9	13
valid_sources[0x73]	50615	1			T1	9		T2	3		T3	21
valid_sources[0x74]	49974	1			T1	10		T2	5		T8	1
valid_sources[0x75]	53085	1			T1	14		T3	1		T9	7
valid_sources[0x76]	53538	1			T1	14		T2	4		T8	13
valid_sources[0x77]	49606	1			T1	16		T2	7		T3	11
valid_sources[0x78]	51269	1			T1	8		T2	5		T9	4
valid_sources[0x79]	136657	1			T1	15		T2	1		T3	18
valid_sources[0x7a]	50119	1			T1	11		T2	1		T3	7
valid_sources[0x7b]	66903	1			T1	12		T2	5		T3	5
valid_sources[0x7c]	55689	1			T1	4		T2	4		T3	11
valid_sources[0x7d]	51921	1			T1	9		T2	4		T3	6
valid_sources[0x7e]	51325	1			T1	12		T2	4		T3	5
valid_sources[0x7f]	50188	1			T1	11		T2	6		T3	1
valid_sources[0x80]	50653	1			T1	5		T2	2		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3368266

1

T1

319

T2

112

T3

264

values[0x0]

all_enables

biggest_size

1866908

1

T1

21

T2

70

T3

21

values[0x1]

all_enables

biggest_size

1790245

1

T1

17

T2

42

T3

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	242370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8790649

1

T1

40

T3

20

T9

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2246384	1			T1	20		T3	10		T9	60
values[0x0]	3296253	1			T1	12		T3	4		T9	27
values[0x1]	3490382	1			T1	8		T3	6		T9	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8945756

1

T1

40

T3

20

T9

120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36307	1			T6	693		T7	4		T14	604
valid_sources[0x01]	35622	1			T6	700		T48	1		T121	1
valid_sources[0x02]	35675	1			T6	636		T17	3		T121	1
valid_sources[0x03]	35290	1			T9	1		T6	701		T7	1
valid_sources[0x04]	36298	1			T9	1		T6	698		T7	4
valid_sources[0x05]	34031	1			T3	1		T6	646		T7	5
valid_sources[0x06]	34792	1			T9	2		T6	692		T17	1
valid_sources[0x07]	34421	1			T6	678		T100	1		T7	3
valid_sources[0x08]	33732	1			T6	753		T17	2		T121	2
valid_sources[0x09]	34553	1			T9	1		T6	725		T7	2
valid_sources[0x0a]	35859	1			T6	736		T121	1		T19	6
valid_sources[0x0b]	35146	1			T6	736		T32	2		T120	1
valid_sources[0x0c]	35561	1			T6	769		T7	2		T110	1
valid_sources[0x0d]	33946	1			T6	638		T32	1		T7	9
valid_sources[0x0e]	35804	1			T6	716		T121	1		T7	5
valid_sources[0x0f]	34902	1			T9	1		T6	728		T32	2
valid_sources[0x10]	34752	1			T6	711		T17	4		T19	7
valid_sources[0x11]	35772	1			T6	671		T17	3		T7	6
valid_sources[0x12]	35115	1			T6	685		T17	2		T7	1
valid_sources[0x13]	34142	1			T6	597		T7	4		T14	663
valid_sources[0x14]	35592	1			T1	1		T5	20		T6	637
valid_sources[0x15]	36747	1			T6	699		T119	1		T121	1
valid_sources[0x16]	33437	1			T3	1		T6	608		T7	1
valid_sources[0x17]	35235	1			T1	3		T6	711		T121	1
valid_sources[0x18]	36791	1			T6	718		T121	3		T7	5
valid_sources[0x19]	34835	1			T9	3		T6	667		T7	2
valid_sources[0x1a]	36602	1			T6	698		T119	1		T19	6
valid_sources[0x1b]	34609	1			T6	636		T121	2		T7	2
valid_sources[0x1c]	35190	1			T6	716		T17	1		T32	1
valid_sources[0x1d]	34631	1			T9	1		T6	724		T119	1
valid_sources[0x1e]	35184	1			T9	3		T6	713		T32	2
valid_sources[0x1f]	35245	1			T9	4		T6	759		T119	1
valid_sources[0x20]	34693	1			T6	721		T119	1		T7	5
valid_sources[0x21]	34357	1			T6	686		T121	2		T7	2
valid_sources[0x22]	36598	1			T1	1		T3	1		T9	1
valid_sources[0x23]	35014	1			T6	710		T17	2		T7	5
valid_sources[0x24]	34692	1			T6	732		T17	1		T32	2
valid_sources[0x25]	34598	1			T6	693		T121	1		T7	4
valid_sources[0x26]	35455	1			T6	682		T121	1		T7	4
valid_sources[0x27]	35437	1			T9	2		T6	713		T7	4
valid_sources[0x28]	36455	1			T6	634		T119	1		T121	1
valid_sources[0x29]	34986	1			T6	730		T121	1		T7	8
valid_sources[0x2a]	35853	1			T6	771		T48	1		T7	6
valid_sources[0x2b]	34283	1			T6	613		T7	2		T14	628
valid_sources[0x2c]	35098	1			T3	1		T6	706		T48	1
valid_sources[0x2d]	36295	1			T6	653		T120	2		T7	2
valid_sources[0x2e]	34891	1			T6	714		T121	2		T7	5
valid_sources[0x2f]	35452	1			T6	648		T7	8		T14	646
valid_sources[0x30]	35366	1			T6	641		T7	10		T14	646
valid_sources[0x31]	35664	1			T6	651		T100	2		T121	1
valid_sources[0x32]	35710	1			T6	696		T121	1		T7	3
valid_sources[0x33]	34236	1			T6	722		T7	2		T110	3
valid_sources[0x34]	35632	1			T6	750		T17	2		T121	1
valid_sources[0x35]	35974	1			T6	773		T32	1		T7	10
valid_sources[0x36]	33162	1			T6	743		T119	1		T121	1
valid_sources[0x37]	35324	1			T6	640		T100	1		T119	3
valid_sources[0x38]	34615	1			T6	660		T14	668		T102	2
valid_sources[0x39]	34378	1			T9	1		T6	647		T119	1
valid_sources[0x3a]	35907	1			T6	676		T32	1		T119	2
valid_sources[0x3b]	35180	1			T6	716		T119	2		T121	2
valid_sources[0x3c]	35374	1			T6	630		T119	1		T121	1
valid_sources[0x3d]	35155	1			T6	697		T119	2		T121	2
valid_sources[0x3e]	37051	1			T6	706		T100	1		T32	1
valid_sources[0x3f]	36403	1			T9	2		T6	741		T48	1
valid_sources[0x40]	35409	1			T6	651		T100	1		T121	2
valid_sources[0x41]	34268	1			T6	660		T119	1		T121	1
valid_sources[0x42]	34942	1			T9	1		T6	702		T121	1
valid_sources[0x43]	33916	1			T6	655		T17	2		T32	2
valid_sources[0x44]	34569	1			T6	666		T119	1		T7	3
valid_sources[0x45]	35193	1			T6	585		T119	1		T121	1
valid_sources[0x46]	35329	1			T9	1		T6	688		T7	7
valid_sources[0x47]	36147	1			T3	1		T6	637		T121	2
valid_sources[0x48]	35642	1			T9	3		T6	709		T7	4
valid_sources[0x49]	35064	1			T6	727		T121	1		T7	6
valid_sources[0x4a]	34879	1			T1	1		T6	721		T7	2
valid_sources[0x4b]	36026	1			T6	714		T7	6		T110	1
valid_sources[0x4c]	35217	1			T6	704		T100	1		T17	1
valid_sources[0x4d]	34838	1			T6	757		T48	1		T121	2
valid_sources[0x4e]	35646	1			T9	2		T6	788		T121	1
valid_sources[0x4f]	35064	1			T6	692		T121	1		T7	3
valid_sources[0x50]	36491	1			T9	1		T6	627		T121	1
valid_sources[0x51]	36015	1			T9	6		T6	663		T119	1
valid_sources[0x52]	35994	1			T6	643		T17	2		T101	160
valid_sources[0x53]	36296	1			T6	664		T7	9		T110	1
valid_sources[0x54]	36881	1			T6	674		T17	2		T121	1
valid_sources[0x55]	35230	1			T9	1		T6	681		T119	2
valid_sources[0x56]	34887	1			T9	1		T6	619		T121	2
valid_sources[0x57]	35315	1			T6	644		T48	1		T7	4
valid_sources[0x58]	36539	1			T6	678		T119	3		T7	3
valid_sources[0x59]	35012	1			T6	689		T7	5		T110	1
valid_sources[0x5a]	35243	1			T6	628		T19	10		T7	6
valid_sources[0x5b]	33901	1			T9	2		T6	680		T7	7
valid_sources[0x5c]	36436	1			T1	2		T6	696		T119	1
valid_sources[0x5d]	35132	1			T6	744		T119	1		T7	4
valid_sources[0x5e]	34708	1			T6	691		T32	1		T119	2
valid_sources[0x5f]	34883	1			T6	622		T19	21		T7	4
valid_sources[0x60]	34761	1			T6	589		T48	1		T121	1
valid_sources[0x61]	35322	1			T6	771		T32	1		T119	1
valid_sources[0x62]	35541	1			T1	1		T6	809		T121	1
valid_sources[0x63]	35437	1			T3	1		T6	750		T119	1
valid_sources[0x64]	36462	1			T6	719		T7	3		T110	1
valid_sources[0x65]	35348	1			T6	686		T119	1		T7	2
valid_sources[0x66]	35380	1			T6	779		T119	2		T121	1
valid_sources[0x67]	33708	1			T6	588		T119	1		T7	3
valid_sources[0x68]	35746	1			T9	1		T6	757		T121	1
valid_sources[0x69]	34583	1			T6	658		T7	1		T110	1
valid_sources[0x6a]	35872	1			T6	709		T7	4		T110	1
valid_sources[0x6b]	34969	1			T1	1		T6	706		T7	8
valid_sources[0x6c]	35438	1			T6	750		T48	1		T7	6
valid_sources[0x6d]	35328	1			T6	730		T7	3		T73	1
valid_sources[0x6e]	34293	1			T1	7		T9	1		T6	683
valid_sources[0x6f]	33630	1			T9	6		T6	599		T119	1
valid_sources[0x70]	34313	1			T1	4		T6	752		T121	1
valid_sources[0x71]	36778	1			T3	1		T9	1		T6	624
valid_sources[0x72]	35637	1			T6	663		T7	7		T110	1
valid_sources[0x73]	34770	1			T6	725		T121	1		T7	3
valid_sources[0x74]	36361	1			T6	664		T121	1		T7	10
valid_sources[0x75]	36073	1			T9	1		T6	686		T17	1
valid_sources[0x76]	34369	1			T6	612		T7	2		T14	662
valid_sources[0x77]	37397	1			T1	1		T6	698		T100	1
valid_sources[0x78]	33977	1			T6	657		T121	2		T7	3
valid_sources[0x79]	36509	1			T6	695		T32	2		T121	1
valid_sources[0x7a]	34728	1			T6	707		T7	7		T110	1
valid_sources[0x7b]	34674	1			T6	714		T19	6		T7	4
valid_sources[0x7c]	35647	1			T6	609		T110	1		T14	674
valid_sources[0x7d]	35267	1			T1	1		T6	719		T119	1
valid_sources[0x7e]	35583	1			T6	715		T7	8		T73	4
valid_sources[0x7f]	35864	1			T6	763		T121	1		T7	3
valid_sources[0x80]	34553	1			T1	3		T6	698		T19	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2233428

1

T1

20

T3

10

T9

60

values[0x0]

all_enables

biggest_size

3279778

1

T1

12

T3

4

T9

27

values[0x1]

all_enables

biggest_size

3277443

1

T1

8

T3

6

T9

33