Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24721910

1

T1

2590

T2

847

T3

784

full_word

8092444

1

T1

357

T2

224

T3

305

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32814064	1			T1	2947		T2	1071		T3	1089
auto[TlIntgErrCmd]	96	1			T276	7		T277	7		T278	9
auto[TlIntgErrData]	97	1			T276	6		T277	4		T278	5
auto[TlIntgErrBoth]	97	1			T276	7		T277	9		T278	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9502979

1

T1

2832

T2

821

T3

975

auto[1]

23311375

1

T1

115

T2

250

T3

114

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6004146	1			T1	2513		T2	709		T3	711
auto[TlIntgErrNone]	partial	auto[1]	18717488	1			T1	77		T2	138		T3	73
auto[TlIntgErrNone]	full_word	auto[0]	3498697	1			T1	319		T2	112		T3	264
auto[TlIntgErrNone]	full_word	auto[1]	4593733	1			T1	38		T2	112		T3	41
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T276	2		T277	3		T278	4
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T276	3		T277	4		T278	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T364	1		T365	1		T366	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T276	2		T367	1		T368	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T276	5		T277	3		T278	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T277	1		T278	3		T367	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T369	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T276	1		T366	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T276	3		T277	5		T278	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T276	4		T277	4		T278	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T370	1		T371	1		-	-