Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	452794679	7911462	0	0
check_regwen_rd_A	452794679	2415	0	0
check_timeout_rd_A	452794679	1997	0	0
check_trigger_regwen_rd_A	452794679	2520	0	0
consistency_check_period_rd_A	452794679	2727	0	0
creator_sw_cfg_read_lock_rd_A	452794679	2187	0	0
direct_access_address_rd_A	452794679	1813	0	0
direct_access_wdata_0_rd_A	452794679	1133	0	0
direct_access_wdata_1_rd_A	452794679	1429	0	0
integrity_check_period_rd_A	452794679	2541	0	0
intr_enable_rd_A	452794679	3176	0	0
owner_sw_cfg_read_lock_rd_A	452794679	2092	0	0
rot_creator_auth_codesign_read_lock_rd_A	452794679	2141	0	0
rot_creator_auth_state_read_lock_rd_A	452794679	2009	0	0
vendor_test_read_lock_rd_A	452794679	1772	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	7911462	0	0
T6	975364	147287	0	0
T14	0	156125	0	0
T15	0	64696	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T20	0	115704	0	0
T21	0	118190	0	0
T22	0	186647	0	0
T23	0	152430	0	0
T31	0	24993	0	0
T32	51825	0	0	0
T42	0	53610	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T268	0	45607	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2415	0	0
T6	975364	176	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	57	0	0
T286	0	37	0	0
T347	0	73	0	0
T348	0	51	0	0
T349	0	76	0	0
T350	0	48	0	0
T351	0	140	0	0
T352	0	22	0	0
T353	0	46	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	1997	0	0
T6	975364	185	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	52	0	0
T286	0	40	0	0
T347	0	69	0	0
T348	0	49	0	0
T349	0	45	0	0
T350	0	24	0	0
T351	0	137	0	0
T352	0	75	0	0
T353	0	30	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2520	0	0
T6	975364	168	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	28	0	0
T286	0	31	0	0
T347	0	102	0	0
T348	0	76	0	0
T349	0	41	0	0
T350	0	39	0	0
T351	0	129	0	0
T352	0	41	0	0
T353	0	58	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2727	0	0
T6	975364	202	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	54	0	0
T286	0	49	0	0
T347	0	118	0	0
T348	0	59	0	0
T349	0	53	0	0
T350	0	18	0	0
T351	0	142	0	0
T352	0	55	0	0
T353	0	74	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2187	0	0
T6	975364	256	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	66	0	0
T286	0	9	0	0
T347	0	53	0	0
T348	0	123	0	0
T349	0	62	0	0
T350	0	55	0	0
T351	0	174	0	0
T352	0	40	0	0
T353	0	38	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	1813	0	0
T6	975364	203	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	36	0	0
T286	0	44	0	0
T347	0	104	0	0
T348	0	66	0	0
T349	0	36	0	0
T350	0	29	0	0
T351	0	173	0	0
T352	0	65	0	0
T353	0	10	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	1133	0	0
T6	975364	112	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	46	0	0
T286	0	6	0	0
T347	0	81	0	0
T348	0	32	0	0
T349	0	48	0	0
T350	0	23	0	0
T351	0	121	0	0
T352	0	21	0	0
T353	0	17	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	1429	0	0
T6	975364	176	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	30	0	0
T286	0	29	0	0
T347	0	42	0	0
T348	0	54	0	0
T349	0	17	0	0
T350	0	48	0	0
T351	0	170	0	0
T352	0	21	0	0
T353	0	21	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2541	0	0
T6	975364	178	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	56	0	0
T286	0	29	0	0
T347	0	75	0	0
T348	0	49	0	0
T349	0	74	0	0
T350	0	65	0	0
T351	0	91	0	0
T352	0	52	0	0
T353	0	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	3176	0	0
T6	975364	177	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	37	0	0
T286	0	56	0	0
T347	0	70	0	0
T348	0	85	0	0
T349	0	77	0	0
T350	0	65	0	0
T351	0	214	0	0
T352	0	20	0	0
T354	0	53	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2092	0	0
T6	975364	172	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	18	0	0
T286	0	30	0	0
T347	0	117	0	0
T348	0	25	0	0
T349	0	84	0	0
T350	0	23	0	0
T351	0	192	0	0
T352	0	48	0	0
T353	0	62	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2141	0	0
T6	975364	179	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	37	0	0
T286	0	32	0	0
T347	0	103	0	0
T348	0	83	0	0
T349	0	72	0	0
T350	0	34	0	0
T351	0	196	0	0
T352	0	32	0	0
T353	0	34	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	2009	0	0
T6	975364	139	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	74	0	0
T286	0	25	0	0
T347	0	59	0	0
T348	0	51	0	0
T349	0	62	0	0
T350	0	41	0	0
T351	0	166	0	0
T352	0	48	0	0
T353	0	31	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452794679	1772	0	0
T6	975364	141	0	0
T17	97371	0	0	0
T18	8532	0	0	0
T32	51825	0	0	0
T48	10844	0	0	0
T60	15231	0	0	0
T98	160026	0	0	0
T99	10210	0	0	0
T100	23290	0	0	0
T101	23321	0	0	0
T264	0	64	0	0
T286	0	24	0	0
T347	0	64	0	0
T348	0	25	0	0
T349	0	44	0	0
T350	0	22	0	0
T351	0	135	0	0
T352	0	45	0	0
T353	0	31	0	0