Module Definition
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Module : prim_edn_req
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_edn_req 98.08 100.00 92.31 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 93.75 100.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.21 94.16 96.15 97.14 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_packer_fifo 74.14 100.00 96.55 100.00 0.00
u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN13911100.00
ALWAYS14333100.00
CONT_ASSIGN14911100.00
ALWAYS16300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
139 1 1
143 1 1
144 1 1
146 1 1
149 1 1
163 unreachable
164 unreachable
165 unreachable
166 unreachable
167 unreachable
168 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_edn_req
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T3,T4

Branch Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 139 3 3 100.00
IF 143 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((req_i && ack_o)) ? -2-: 139 (word_ack) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T4
0 1 Covered T1,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 143 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_edn_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOutputDiffFromPrev_A 449862962 252410777 0 0
DataOutputValid_A 449862962 254010 0 0


DataOutputDiffFromPrev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449862962 252410777 0 0
T1 24042 6197 0 0
T2 9637 0 0 0
T3 20939 13517 0 0
T4 0 570406 0 0
T5 15417 0 0 0
T6 0 157047 0 0
T8 11937 0 0 0
T9 23647 0 0 0
T10 11375 0 0 0
T11 18983 0 0 0
T12 5982 0 0 0
T13 16807 0 0 0
T17 0 47668 0 0
T19 0 41213 0 0
T32 0 22336 0 0
T98 0 116930 0 0
T119 0 10119 0 0
T120 0 12800 0 0

DataOutputValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449862962 254010 0 0
T1 24042 94 0 0
T2 9637 0 0 0
T3 20939 92 0 0
T4 0 362 0 0
T5 15417 0 0 0
T6 0 707 0 0
T8 11937 0 0 0
T9 23647 0 0 0
T10 11375 0 0 0
T11 18983 0 0 0
T12 5982 0 0 0
T13 16807 0 0 0
T17 0 67 0 0
T19 0 426 0 0
T32 0 72 0 0
T98 0 232 0 0
T119 0 94 0 0
T120 0 92 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%